Aaron Williams | b2ea818 | 2020-06-30 12:08:56 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2020 Marvell International Ltd. |
| 4 | */ |
| 5 | |
| 6 | #include <asm/global_data.h> |
| 7 | #include <linux/bitfield.h> |
| 8 | #include <linux/bitops.h> |
| 9 | #include <linux/compat.h> |
| 10 | #include <linux/io.h> |
| 11 | #include <mach/clock.h> |
| 12 | #include <mach/cavm-reg.h> |
| 13 | |
| 14 | DECLARE_GLOBAL_DATA_PTR; |
| 15 | |
Stefan Roese | 72a49ef | 2020-08-24 13:04:39 +0200 | [diff] [blame] | 16 | /* |
| 17 | * TRUE for devices having registers with little-endian byte |
| 18 | * order, FALSE for registers with native-endian byte order. |
| 19 | * PCI mandates little-endian, USB and SATA are configurable, |
| 20 | * but we chose little-endian for these. |
| 21 | * |
| 22 | * This table will be referened in the Octeon platform specific |
| 23 | * mangle-port.h header. |
| 24 | */ |
| 25 | const bool octeon_should_swizzle_table[256] = { |
| 26 | [0x00] = true, /* bootbus/CF */ |
| 27 | [0x1b] = true, /* PCI mmio window */ |
| 28 | [0x1c] = true, /* PCI mmio window */ |
| 29 | [0x1d] = true, /* PCI mmio window */ |
| 30 | [0x1e] = true, /* PCI mmio window */ |
| 31 | [0x68] = true, /* OCTEON III USB */ |
| 32 | [0x69] = true, /* OCTEON III USB */ |
| 33 | [0x6c] = true, /* OCTEON III SATA */ |
| 34 | [0x6f] = true, /* OCTEON II USB */ |
| 35 | }; |
| 36 | |
Aaron Williams | b2ea818 | 2020-06-30 12:08:56 +0200 | [diff] [blame] | 37 | static int get_clocks(void) |
| 38 | { |
| 39 | const u64 ref_clock = PLL_REF_CLK; |
| 40 | void __iomem *rst_boot; |
| 41 | u64 val; |
| 42 | |
| 43 | rst_boot = ioremap(CAVM_RST_BOOT, 0); |
| 44 | val = ioread64(rst_boot); |
| 45 | gd->cpu_clk = ref_clock * FIELD_GET(RST_BOOT_C_MUL, val); |
| 46 | gd->bus_clk = ref_clock * FIELD_GET(RST_BOOT_PNR_MUL, val); |
| 47 | |
| 48 | debug("%s: cpu: %lu, bus: %lu\n", __func__, gd->cpu_clk, gd->bus_clk); |
| 49 | |
| 50 | return 0; |
| 51 | } |
| 52 | |
| 53 | /* Early mach init code run from flash */ |
| 54 | int mach_cpu_init(void) |
| 55 | { |
| 56 | void __iomem *mio_boot_reg_cfg0; |
| 57 | |
| 58 | /* Remap boot-bus 0x1fc0.0000 -> 0x1f40.0000 */ |
| 59 | /* ToDo: Move this to an early running bus (bootbus) DM driver */ |
| 60 | mio_boot_reg_cfg0 = ioremap(CAVM_MIO_BOOT_REG_CFG0, 0); |
| 61 | clrsetbits_be64(mio_boot_reg_cfg0, 0xffff, 0x1f40); |
| 62 | |
| 63 | /* Get clocks and store them in GD */ |
| 64 | get_clocks(); |
| 65 | |
| 66 | return 0; |
| 67 | } |
| 68 | |
| 69 | /** |
| 70 | * Returns number of cores |
| 71 | * |
| 72 | * @return number of CPU cores for the specified node |
| 73 | */ |
| 74 | static int cavm_octeon_num_cores(void) |
| 75 | { |
| 76 | void __iomem *ciu_fuse; |
| 77 | |
| 78 | ciu_fuse = ioremap(CAVM_CIU_FUSE, 0); |
| 79 | return fls64(ioread64(ciu_fuse) & 0xffffffffffff); |
| 80 | } |
| 81 | |
| 82 | int print_cpuinfo(void) |
| 83 | { |
| 84 | printf("SoC: Octeon CN73xx (%d cores)\n", cavm_octeon_num_cores()); |
| 85 | |
| 86 | return 0; |
| 87 | } |