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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Patrick Delaunay85b53972018-03-12 10:46:10 +01002/*
3 * (C) Copyright 2016
4 * Vikas Manocha, <vikas.manocha@st.com>
Patrick Delaunay85b53972018-03-12 10:46:10 +01005 */
6
7#ifndef _STM32_GPIO_H_
8#define _STM32_GPIO_H_
9#include <asm/gpio.h>
10
Patrice Chotard20ddb322018-12-03 10:52:52 +010011#define STM32_GPIOS_PER_BANK 16
12
Patrick Delaunay85b53972018-03-12 10:46:10 +010013enum stm32_gpio_port {
14 STM32_GPIO_PORT_A = 0,
15 STM32_GPIO_PORT_B,
16 STM32_GPIO_PORT_C,
17 STM32_GPIO_PORT_D,
18 STM32_GPIO_PORT_E,
19 STM32_GPIO_PORT_F,
20 STM32_GPIO_PORT_G,
21 STM32_GPIO_PORT_H,
22 STM32_GPIO_PORT_I
23};
24
25enum stm32_gpio_pin {
26 STM32_GPIO_PIN_0 = 0,
27 STM32_GPIO_PIN_1,
28 STM32_GPIO_PIN_2,
29 STM32_GPIO_PIN_3,
30 STM32_GPIO_PIN_4,
31 STM32_GPIO_PIN_5,
32 STM32_GPIO_PIN_6,
33 STM32_GPIO_PIN_7,
34 STM32_GPIO_PIN_8,
35 STM32_GPIO_PIN_9,
36 STM32_GPIO_PIN_10,
37 STM32_GPIO_PIN_11,
38 STM32_GPIO_PIN_12,
39 STM32_GPIO_PIN_13,
40 STM32_GPIO_PIN_14,
41 STM32_GPIO_PIN_15
42};
43
44enum stm32_gpio_mode {
45 STM32_GPIO_MODE_IN = 0,
46 STM32_GPIO_MODE_OUT,
47 STM32_GPIO_MODE_AF,
48 STM32_GPIO_MODE_AN
49};
50
51enum stm32_gpio_otype {
52 STM32_GPIO_OTYPE_PP = 0,
53 STM32_GPIO_OTYPE_OD
54};
55
56enum stm32_gpio_speed {
57 STM32_GPIO_SPEED_2M = 0,
58 STM32_GPIO_SPEED_25M,
59 STM32_GPIO_SPEED_50M,
60 STM32_GPIO_SPEED_100M
61};
62
63enum stm32_gpio_pupd {
64 STM32_GPIO_PUPD_NO = 0,
65 STM32_GPIO_PUPD_UP,
66 STM32_GPIO_PUPD_DOWN
67};
68
69enum stm32_gpio_af {
70 STM32_GPIO_AF0 = 0,
71 STM32_GPIO_AF1,
72 STM32_GPIO_AF2,
73 STM32_GPIO_AF3,
74 STM32_GPIO_AF4,
75 STM32_GPIO_AF5,
76 STM32_GPIO_AF6,
77 STM32_GPIO_AF7,
78 STM32_GPIO_AF8,
79 STM32_GPIO_AF9,
80 STM32_GPIO_AF10,
81 STM32_GPIO_AF11,
82 STM32_GPIO_AF12,
83 STM32_GPIO_AF13,
84 STM32_GPIO_AF14,
85 STM32_GPIO_AF15
86};
87
88struct stm32_gpio_dsc {
89 enum stm32_gpio_port port;
90 enum stm32_gpio_pin pin;
91};
92
93struct stm32_gpio_ctl {
94 enum stm32_gpio_mode mode;
95 enum stm32_gpio_otype otype;
96 enum stm32_gpio_speed speed;
97 enum stm32_gpio_pupd pupd;
98 enum stm32_gpio_af af;
99};
100
101struct stm32_gpio_regs {
102 u32 moder; /* GPIO port mode */
103 u32 otyper; /* GPIO port output type */
104 u32 ospeedr; /* GPIO port output speed */
105 u32 pupdr; /* GPIO port pull-up/pull-down */
106 u32 idr; /* GPIO port input data */
107 u32 odr; /* GPIO port output data */
108 u32 bsrr; /* GPIO port bit set/reset */
109 u32 lckr; /* GPIO port configuration lock */
110 u32 afr[2]; /* GPIO alternate function */
111};
112
113struct stm32_gpio_priv {
114 struct stm32_gpio_regs *regs;
Patrice Chotard0099c1e2018-12-03 10:52:51 +0100115 unsigned int gpio_range;
Patrick Delaunay85b53972018-03-12 10:46:10 +0100116};
Patrice Chotard0099c1e2018-12-03 10:52:51 +0100117
118int stm32_offset_to_index(struct udevice *dev, unsigned int offset);
119
Patrick Delaunay85b53972018-03-12 10:46:10 +0100120#endif /* _STM32_GPIO_H_ */