| Daniel Hellstrom | 9d7c6b2 | 2008-03-28 09:47:00 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2008, |
| 3 | * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. |
| 4 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| Daniel Hellstrom | 9d7c6b2 | 2008-03-28 09:47:00 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __SPARC_CACHE_H__ |
| 9 | #define __SPARC_CACHE_H__ |
| 10 | |
| Daniel Hellstrom | 9d7c6b2 | 2008-03-28 09:47:00 +0100 | [diff] [blame] | 11 | #include <asm/processor.h> |
| 12 | |
| Anton Staaf | fb2df08 | 2011-10-17 16:46:08 -0700 | [diff] [blame] | 13 | /* |
| 14 | * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise |
| 15 | * use 32-bytes, the cacheline size for Sparc. |
| 16 | */ |
| 17 | #ifdef CONFIG_SYS_CACHELINE_SIZE |
| 18 | #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE |
| 19 | #else |
| 20 | #define ARCH_DMA_MINALIGN 32 |
| 21 | #endif |
| 22 | |
| Daniel Hellstrom | 9d7c6b2 | 2008-03-28 09:47:00 +0100 | [diff] [blame] | 23 | #endif |