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David Wu5f596ae2019-01-02 21:00:55 +08001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4 */
5
6#ifndef __DRIVERS_PINCTRL_ROCKCHIP_H
7#define __DRIVERS_PINCTRL_ROCKCHIP_H
8
Simon Glass4dcacfc2020-05-10 11:40:13 -06009#include <linux/bitops.h>
David Wu5f596ae2019-01-02 21:00:55 +080010#include <linux/types.h>
11
Jagan Teki9e0e6812022-12-14 23:20:56 +053012#define RK_GENMASK_VAL(h, l, v) \
13 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
14
David Wu5f596ae2019-01-02 21:00:55 +080015/**
16 * Encode variants of iomux registers into a type variable
17 */
18#define IOMUX_GPIO_ONLY BIT(0)
19#define IOMUX_WIDTH_4BIT BIT(1)
20#define IOMUX_SOURCE_PMU BIT(2)
21#define IOMUX_UNROUTED BIT(3)
22#define IOMUX_WIDTH_3BIT BIT(4)
David Wufd2fdf72019-12-03 19:26:50 +080023#define IOMUX_8WIDTH_2BIT BIT(5)
Jagan Teki9e0e6812022-12-14 23:20:56 +053024#define IOMUX_L_SOURCE_PMU BIT(6)
David Wu5f596ae2019-01-02 21:00:55 +080025
26/**
27 * Defined some common pins constants
28 */
29#define ROCKCHIP_PULL_BITS_PER_PIN 2
30#define ROCKCHIP_PULL_PINS_PER_REG 8
31#define ROCKCHIP_PULL_BANK_STRIDE 16
32#define ROCKCHIP_DRV_BITS_PER_PIN 2
33#define ROCKCHIP_DRV_PINS_PER_REG 8
34#define ROCKCHIP_DRV_BANK_STRIDE 16
35#define ROCKCHIP_DRV_3BITS_PER_PIN 3
36
37/**
38 * @type: iomux variant using IOMUX_* constants
39 * @offset: if initialized to -1 it will be autocalculated, by specifying
40 * an initial offset value the relevant source offset can be reset
41 * to a new value for autocalculating the following iomux registers.
42 */
43struct rockchip_iomux {
44 int type;
45 int offset;
46};
47
48/**
49 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
50 */
51enum rockchip_pin_drv_type {
52 DRV_TYPE_IO_DEFAULT = 0,
53 DRV_TYPE_IO_1V8_OR_3V0,
54 DRV_TYPE_IO_1V8_ONLY,
55 DRV_TYPE_IO_1V8_3V0_AUTO,
56 DRV_TYPE_IO_3V3_ONLY,
57 DRV_TYPE_MAX
58};
59
60/**
61 * enum type index corresponding to rockchip_pull_list arrays index.
62 */
63enum rockchip_pin_pull_type {
64 PULL_TYPE_IO_DEFAULT = 0,
65 PULL_TYPE_IO_1V8_ONLY,
66 PULL_TYPE_MAX
67};
68
69/**
Jagan Teki9e0e6812022-12-14 23:20:56 +053070 * Rockchip pinctrl route type
71 *
72 * DEFAULT : Same regmap as pin iomux
73 * TOPGRF : Mux route setting in topgrf
74 * PMUGRF : Mux route setting in pmugrf
75 * INVALID : Nnot need to set mux route
76 */
77enum rockchip_pin_route_type {
78 ROUTE_TYPE_DEFAULT = 0,
79 ROUTE_TYPE_TOPGRF = 1,
80 ROUTE_TYPE_PMUGRF = 2,
81
82 ROUTE_TYPE_INVALID = -1,
83};
84
85/**
David Wu5f596ae2019-01-02 21:00:55 +080086 * @drv_type: drive strength variant using rockchip_perpin_drv_type
87 * @offset: if initialized to -1 it will be autocalculated, by specifying
88 * an initial offset value the relevant source offset can be reset
89 * to a new value for autocalculating the following drive strength
90 * registers. if used chips own cal_drv func instead to calculate
91 * registers offset, the variant could be ignored.
92 */
93struct rockchip_drv {
94 enum rockchip_pin_drv_type drv_type;
95 int offset;
96};
97
98/**
99 * @priv: common pinctrl private basedata
100 * @pin_base: first pin number
101 * @nr_pins: number of pins in this bank
102 * @name: name of the bank
103 * @bank_num: number of the bank, to account for holes
104 * @iomux: array describing the 4 iomux sources of the bank
105 * @drv: array describing the 4 drive strength sources of the bank
106 * @pull_type: array describing the 4 pull type sources of the bank
107 * @recalced_mask: bits describing the mux recalced pins of per bank
108 * @route_mask: bits describing the routing pins of per bank
109 */
110struct rockchip_pin_bank {
111 struct rockchip_pinctrl_priv *priv;
112 u32 pin_base;
113 u8 nr_pins;
114 char *name;
115 u8 bank_num;
116 struct rockchip_iomux iomux[4];
117 struct rockchip_drv drv[4];
118 enum rockchip_pin_pull_type pull_type[4];
119 u32 recalced_mask;
120 u32 route_mask;
121};
122
123#define PIN_BANK(id, pins, label) \
124 { \
125 .bank_num = id, \
126 .nr_pins = pins, \
127 .name = label, \
128 .iomux = { \
129 { .offset = -1 }, \
130 { .offset = -1 }, \
131 { .offset = -1 }, \
132 { .offset = -1 }, \
133 }, \
134 }
135
136#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
137 { \
138 .bank_num = id, \
139 .nr_pins = pins, \
140 .name = label, \
141 .iomux = { \
142 { .type = iom0, .offset = -1 }, \
143 { .type = iom1, .offset = -1 }, \
144 { .type = iom2, .offset = -1 }, \
145 { .type = iom3, .offset = -1 }, \
146 }, \
147 }
148
Jagan Teki9e0e6812022-12-14 23:20:56 +0530149#define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \
150 iom3, offset0, offset1, offset2, \
151 offset3) \
152 { \
153 .bank_num = id, \
154 .nr_pins = pins, \
155 .name = label, \
156 .iomux = { \
157 { .type = iom0, .offset = offset0 }, \
158 { .type = iom1, .offset = offset1 }, \
159 { .type = iom2, .offset = offset2 }, \
160 { .type = iom3, .offset = offset3 }, \
161 }, \
162 }
163
David Wu5f596ae2019-01-02 21:00:55 +0800164#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
165 { \
166 .bank_num = id, \
167 .nr_pins = pins, \
168 .name = label, \
169 .iomux = { \
170 { .offset = -1 }, \
171 { .offset = -1 }, \
172 { .offset = -1 }, \
173 { .offset = -1 }, \
174 }, \
175 .drv = { \
176 { .drv_type = type0, .offset = -1 }, \
177 { .drv_type = type1, .offset = -1 }, \
178 { .drv_type = type2, .offset = -1 }, \
179 { .drv_type = type3, .offset = -1 }, \
180 }, \
181 }
182
183#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
184 drv2, drv3, pull0, pull1, \
185 pull2, pull3) \
186 { \
187 .bank_num = id, \
188 .nr_pins = pins, \
189 .name = label, \
190 .iomux = { \
191 { .offset = -1 }, \
192 { .offset = -1 }, \
193 { .offset = -1 }, \
194 { .offset = -1 }, \
195 }, \
196 .drv = { \
197 { .drv_type = drv0, .offset = -1 }, \
198 { .drv_type = drv1, .offset = -1 }, \
199 { .drv_type = drv2, .offset = -1 }, \
200 { .drv_type = drv3, .offset = -1 }, \
201 }, \
202 .pull_type[0] = pull0, \
203 .pull_type[1] = pull1, \
204 .pull_type[2] = pull2, \
205 .pull_type[3] = pull3, \
206 }
207
208#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
209 iom2, iom3, drv0, drv1, drv2, \
210 drv3, offset0, offset1, \
211 offset2, offset3) \
212 { \
213 .bank_num = id, \
214 .nr_pins = pins, \
215 .name = label, \
216 .iomux = { \
217 { .type = iom0, .offset = -1 }, \
218 { .type = iom1, .offset = -1 }, \
219 { .type = iom2, .offset = -1 }, \
220 { .type = iom3, .offset = -1 }, \
221 }, \
222 .drv = { \
223 { .drv_type = drv0, .offset = offset0 }, \
224 { .drv_type = drv1, .offset = offset1 }, \
225 { .drv_type = drv2, .offset = offset2 }, \
226 { .drv_type = drv3, .offset = offset3 }, \
227 }, \
David Wu5f596ae2019-01-02 21:00:55 +0800228 }
229
230#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
231 label, iom0, iom1, iom2, \
232 iom3, drv0, drv1, drv2, \
233 drv3, offset0, offset1, \
234 offset2, offset3, pull0, \
235 pull1, pull2, pull3) \
236 { \
237 .bank_num = id, \
238 .nr_pins = pins, \
239 .name = label, \
240 .iomux = { \
241 { .type = iom0, .offset = -1 }, \
242 { .type = iom1, .offset = -1 }, \
243 { .type = iom2, .offset = -1 }, \
244 { .type = iom3, .offset = -1 }, \
245 }, \
246 .drv = { \
247 { .drv_type = drv0, .offset = offset0 }, \
248 { .drv_type = drv1, .offset = offset1 }, \
249 { .drv_type = drv2, .offset = offset2 }, \
250 { .drv_type = drv3, .offset = offset3 }, \
251 }, \
252 .pull_type[0] = pull0, \
253 .pull_type[1] = pull1, \
254 .pull_type[2] = pull2, \
255 .pull_type[3] = pull3, \
256 }
257
Jagan Teki9e0e6812022-12-14 23:20:56 +0530258#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
259 { \
260 .bank_num = ID, \
261 .pin = PIN, \
262 .func = FUNC, \
263 .route_offset = REG, \
264 .route_val = VAL, \
265 .route_type = FLAG, \
266 }
267
268#define MR_DEFAULT(ID, PIN, FUNC, REG, VAL) \
269 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_DEFAULT)
270
271#define MR_TOPGRF(ID, PIN, FUNC, REG, VAL) \
272 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_TOPGRF)
273
274#define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \
275 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF)
276
David Wu5f596ae2019-01-02 21:00:55 +0800277/**
278 * struct rockchip_mux_recalced_data: recalculate a pin iomux data.
279 * @num: bank number.
280 * @pin: pin number.
281 * @reg: register offset.
282 * @bit: index at register.
283 * @mask: mask bit
284 */
285struct rockchip_mux_recalced_data {
286 u8 num;
287 u8 pin;
288 u32 reg;
289 u8 bit;
290 u8 mask;
291};
292
293/**
294 * struct rockchip_mux_route_data: route a pin iomux data.
295 * @bank_num: bank number.
296 * @pin: index at register or used to calc index.
297 * @func: the min pin.
Jagan Teki9e0e6812022-12-14 23:20:56 +0530298 * @route_type: the register type.
David Wu5f596ae2019-01-02 21:00:55 +0800299 * @route_offset: the max pin.
300 * @route_val: the register offset.
301 */
302struct rockchip_mux_route_data {
303 u8 bank_num;
304 u8 pin;
305 u8 func;
Jagan Teki9e0e6812022-12-14 23:20:56 +0530306 enum rockchip_pin_route_type route_type : 8;
David Wu5f596ae2019-01-02 21:00:55 +0800307 u32 route_offset;
308 u32 route_val;
309};
310
311/**
312 */
313struct rockchip_pin_ctrl {
314 struct rockchip_pin_bank *pin_banks;
315 u32 nr_banks;
316 u32 nr_pins;
David Wu5f596ae2019-01-02 21:00:55 +0800317 int grf_mux_offset;
318 int pmu_mux_offset;
319 int grf_drv_offset;
320 int pmu_drv_offset;
321 struct rockchip_mux_recalced_data *iomux_recalced;
322 u32 niomux_recalced;
323 struct rockchip_mux_route_data *iomux_routes;
324 u32 niomux_routes;
325
David Wu3dd7d6c2019-04-16 21:50:55 +0800326 int (*set_mux)(struct rockchip_pin_bank *bank,
327 int pin, int mux);
David Wu2972c452019-04-16 21:57:05 +0800328 int (*set_pull)(struct rockchip_pin_bank *bank,
329 int pin_num, int pull);
David Wu40a55482019-04-16 21:55:26 +0800330 int (*set_drive)(struct rockchip_pin_bank *bank,
331 int pin_num, int strength);
David Wu7ae4ec92019-04-16 21:58:13 +0800332 int (*set_schmitt)(struct rockchip_pin_bank *bank,
333 int pin_num, int enable);
David Wu5f596ae2019-01-02 21:00:55 +0800334};
335
336/**
337 */
338struct rockchip_pinctrl_priv {
339 struct rockchip_pin_ctrl *ctrl;
340 struct regmap *regmap_base;
341 struct regmap *regmap_pmu;
342};
343
344extern const struct pinctrl_ops rockchip_pinctrl_ops;
345int rockchip_pinctrl_probe(struct udevice *dev);
David Wu3dd7d6c2019-04-16 21:50:55 +0800346void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
347 int *reg, u8 *bit, int *mask);
David Wu3dd7d6c2019-04-16 21:50:55 +0800348int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask);
David Wu40a55482019-04-16 21:55:26 +0800349int rockchip_translate_drive_value(int type, int strength);
David Wu2972c452019-04-16 21:57:05 +0800350int rockchip_translate_pull_value(int type, int pull);
David Wu5f596ae2019-01-02 21:00:55 +0800351
352#endif /* __DRIVERS_PINCTRL_ROCKCHIP_H */