blob: 3a83e4dc1ca3822686005e2d591c1b661bd277f0 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Calvin Johnson2deb8c92018-03-08 15:30:27 +05302/*
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017 NXP
Calvin Johnson2deb8c92018-03-08 15:30:27 +05305 */
6
7#ifndef _BMU_H_
8#define _BMU_H_
9
10#define BMU_VERSION 0x000
11#define BMU_CTRL 0x004
12#define BMU_UCAST_CONFIG 0x008
13#define BMU_UCAST_BASE_ADDR 0x00c
14#define BMU_BUF_SIZE 0x010
15#define BMU_BUF_CNT 0x014
16#define BMU_THRES 0x018
17#define BMU_INT_SRC 0x020
18#define BMU_INT_ENABLE 0x024
19#define BMU_ALLOC_CTRL 0x030
20#define BMU_FREE_CTRL 0x034
21#define BMU_FREE_ERR_ADDR 0x038
22#define BMU_CURR_BUF_CNT 0x03c
23#define BMU_MCAST_CNT 0x040
24#define BMU_MCAST_ALLOC_CTRL 0x044
25#define BMU_REM_BUF_CNT 0x048
26#define BMU_LOW_WATERMARK 0x050
27#define BMU_HIGH_WATERMARK 0x054
28#define BMU_INT_MEM_ACCESS 0x100
29
30struct bmu_cfg {
31 u32 baseaddr;
32 u32 count;
33 u32 size;
34};
35
36#define BMU1_BUF_SIZE LMEM_BUF_SIZE_LN2
37#define BMU2_BUF_SIZE DDR_BUF_SIZE_LN2
38
39#endif /* _BMU_H_ */