Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Common AM625 SK dts file for SPLs |
| 4 | * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ |
| 5 | */ |
| 6 | |
| 7 | / { |
| 8 | chosen { |
| 9 | stdout-path = "serial2:115200n8"; |
| 10 | tick-timer = &timer1; |
| 11 | }; |
| 12 | |
| 13 | aliases { |
| 14 | mmc1 = &sdhci1; |
| 15 | }; |
Georgi Vlaev | e9c68bf | 2022-06-14 17:45:31 +0300 | [diff] [blame] | 16 | |
| 17 | memory@80000000 { |
| 18 | u-boot,dm-spl; |
| 19 | }; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 20 | }; |
| 21 | |
| 22 | &cbass_main{ |
| 23 | u-boot,dm-spl; |
| 24 | |
| 25 | timer1: timer@2400000 { |
| 26 | compatible = "ti,omap5430-timer"; |
| 27 | reg = <0x00 0x2400000 0x00 0x80>; |
| 28 | ti,timer-alwon; |
| 29 | clock-frequency = <25000000>; |
| 30 | u-boot,dm-spl; |
| 31 | }; |
| 32 | }; |
| 33 | |
| 34 | &dmss { |
| 35 | u-boot,dm-spl; |
| 36 | }; |
| 37 | |
| 38 | &secure_proxy_main { |
| 39 | u-boot,dm-spl; |
| 40 | }; |
| 41 | |
| 42 | &dmsc { |
| 43 | u-boot,dm-spl; |
| 44 | }; |
| 45 | |
| 46 | &k3_pds { |
| 47 | u-boot,dm-spl; |
| 48 | }; |
| 49 | |
| 50 | &k3_clks { |
| 51 | u-boot,dm-spl; |
| 52 | }; |
| 53 | |
| 54 | &k3_reset { |
| 55 | u-boot,dm-spl; |
| 56 | }; |
| 57 | |
| 58 | &wkup_conf { |
| 59 | u-boot,dm-spl; |
| 60 | }; |
| 61 | |
| 62 | &chipid { |
| 63 | u-boot,dm-spl; |
| 64 | }; |
| 65 | |
| 66 | &main_pmx0 { |
| 67 | u-boot,dm-spl; |
| 68 | }; |
| 69 | |
| 70 | &main_uart0 { |
| 71 | u-boot,dm-spl; |
| 72 | }; |
| 73 | |
| 74 | &main_uart0_pins_default { |
| 75 | u-boot,dm-spl; |
| 76 | }; |
| 77 | |
| 78 | &main_uart1 { |
| 79 | u-boot,dm-spl; |
| 80 | }; |
| 81 | |
| 82 | &cbass_mcu { |
| 83 | u-boot,dm-spl; |
| 84 | }; |
| 85 | |
| 86 | &cbass_wakeup { |
| 87 | u-boot,dm-spl; |
| 88 | }; |
| 89 | |
| 90 | &mcu_pmx0 { |
| 91 | u-boot,dm-spl; |
| 92 | }; |
| 93 | |
| 94 | &wkup_uart0 { |
| 95 | u-boot,dm-spl; |
| 96 | }; |
| 97 | |
| 98 | &sdhci1 { |
| 99 | u-boot,dm-spl; |
| 100 | }; |
| 101 | |
| 102 | &main_mmc1_pins_default { |
| 103 | u-boot,dm-spl; |
| 104 | }; |
Dhruva Gole | 0f33ef2 | 2022-10-27 20:23:10 +0530 | [diff] [blame] | 105 | |
| 106 | &fss { |
| 107 | u-boot,dm-spl; |
| 108 | }; |
| 109 | |
| 110 | &ospi0_pins_default { |
| 111 | u-boot,dm-spl; |
| 112 | }; |
| 113 | |
| 114 | &ospi0 { |
| 115 | u-boot,dm-spl; |
| 116 | |
| 117 | flash@0 { |
| 118 | u-boot,dm-spl; |
| 119 | |
| 120 | partitions { |
| 121 | u-boot,dm-spl; |
| 122 | |
| 123 | partition@3fc0000 { |
| 124 | u-boot,dm-spl; |
| 125 | }; |
| 126 | }; |
| 127 | }; |
| 128 | }; |
Sjoerd Simons | 7fb6d4a | 2022-12-20 16:21:45 +0100 | [diff] [blame] | 129 | |
| 130 | &cpsw3g { |
| 131 | reg = <0x0 0x8000000 0x0 0x200000>, |
| 132 | <0x0 0x43000200 0x0 0x8>; |
| 133 | reg-names = "cpsw_nuss", "mac_efuse"; |
| 134 | /delete-property/ ranges; |
| 135 | u-boot,dm-spl; |
| 136 | |
| 137 | cpsw-phy-sel@04044 { |
| 138 | compatible = "ti,am64-phy-gmii-sel"; |
| 139 | reg = <0x0 0x00104044 0x0 0x8>; |
| 140 | u-boot,dm-spl; |
| 141 | }; |
| 142 | }; |
| 143 | |
| 144 | &cpsw_port1 { |
| 145 | u-boot,dm-spl; |
| 146 | }; |
| 147 | |
| 148 | &cpsw_port2 { |
| 149 | status = "disabled"; |
| 150 | }; |