blob: 62116faafa3d746f6015f9b7fd21df21cc00fbeb [file] [log] [blame]
Simon Goldschmidt15616b52018-11-02 11:54:52 +01001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * U-Boot additions
4 *
5 * Copyright (C) 2013 Altera Corporation <www.altera.com>
6 * Copyright (c) 2018 Simon Goldschmidt
7 */
8
Simon Goldschmidt64a12bf2019-03-01 20:12:29 +01009#include "socfpga-common-u-boot.dtsi"
10
Simon Goldschmidt15616b52018-11-02 11:54:52 +010011/{
12 aliases {
13 spi0 = "/soc/spi@ff705000";
14 udc0 = &usb1;
15 };
Simon Goldschmidt15616b52018-11-02 11:54:52 +010016};
17
18&watchdog0 {
19 status = "disabled";
20};
21
22&mmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -070023 bootph-all;
Simon Goldschmidt15616b52018-11-02 11:54:52 +010024};
25
26&qspi {
Simon Glassd3a98cb2023-02-13 08:56:33 -070027 bootph-all;
Simon Goldschmidt15616b52018-11-02 11:54:52 +010028};
29
30&flash {
Neil Armstronga009fa72019-02-10 10:16:20 +000031 compatible = "n25q00", "jedec,spi-nor";
Simon Glassd3a98cb2023-02-13 08:56:33 -070032 bootph-all;
Simon Goldschmidt15616b52018-11-02 11:54:52 +010033};
34
35&uart0 {
36 clock-frequency = <100000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -070037 bootph-all;
Simon Goldschmidt15616b52018-11-02 11:54:52 +010038};
39
40&uart1 {
41 clock-frequency = <100000000>;
42};
43
44&porta {
45 bank-name = "porta";
46};
47
48&portb {
49 bank-name = "portb";
50};
51
52&portc {
53 bank-name = "portc";
54};