Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 5c6926c9d6d99dae20ce69d1aa4ab234b46fb8b9 / . / arch / arm / dts / imx8qm-cgtqmx8.dts
blob: 919d00644ff3690a2be754ed07ddb3da91ae0a7b [file] [log] [blame]
Oliver Grauteaf5e29b2021-05-31 15:50:40 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017 NXP
5 * Copyright 2017 congatec AG
6 * Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com>
7 */
8
9/dts-v1/;
10
11/* First 128KB is for PSCI ATF. */
12/memreserve/ 0x80000000 0x00020000;
13
14#include "fsl-imx8qm.dtsi"
Oliver Graute51039ce2022-11-04 16:03:38 +0100[diff] [blame]15#include "imx8qm-u-boot.dtsi"
Oliver Grauteaf5e29b2021-05-31 15:50:40 +0200[diff] [blame]16
17/ {
18 model = "Congatec QMX8 Qseven series";
19 compatible = "fsl,imx8qm-qmx8", "fsl,imx8qm";
20
21 chosen {
22 bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
23 stdout-path = &lpuart0;
24 };
25
26 regulators {
27 compatible = "simple-bus";
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 reg_usdhc2_vmmc: usdhc2_vmmc {
32 compatible = "regulator-fixed";
33 regulator-name = "sw-3p3-sd1";
34 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <3300000>;
36 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
37 enable-active-high;
38 off-on-delay-us = <3000>;
39 };
40
41 reg_usdhc3_vmmc: usdhc3_vmmc {
42 compatible = "regulator-fixed";
43 regulator-name = "sw-3p3-sd2";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>;
47 enable-active-high;
48 off-on-delay-us = <3000>;
49 };
50 };
51};
52
53&fec1 {
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_fec1>;
56 phy-mode = "rgmii";
57 phy-handle = <&ethphy0>;
58 fsl,magic-packet;
59 fsl,rgmii_txc_dly;
60 fsl,rgmii_rxc_dly;
61 status = "okay";
62
63 mdio {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 ethphy0: ethernet-phy@6 {
68 compatible = "ethernet-phy-ieee802.3-c22";
69 reg = <6>;
70 at803x,eee-disabled;
71 at803x,vddio-1p8v;
72 };
73 };
74};
75
76&gpio2 {
77 status = "okay";
78};
79
80&gpio5 {
81 status = "okay";
82};
83
84&i2c0 {
85 #address-cells = <1>;
86 #size-cells = <0>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_lpi2c0>;
89 clock-frequency = <100000>;
90 status = "okay";
91
92 rtc_ext: m41t62@68 {
93 compatible = "st,m41t62";
94 reg = <0x68>;
95 };
96};
97
98&i2c1 {
99 #address-cells = <1>;
100 #size-cells = <0>;
101 clock-frequency = <100000>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_lpi2c1>;
104 status = "okay";
105
106 wm8904: wm8904@1a {
107 compatible = "wlf,wm8904";
108 reg = <0x1a>;
109
110 clocks = <&clk IMX8QM_AUD_MCLKOUT0>;
111 clock-names = "mclk";
112 wlf,shared-lrclk;
113 /* power-domains = <&pd_mclk_out0>; */
114
115 assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>,
116 <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
117 <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
118 <&clk IMX8QM_AUD_MCLKOUT0>;
119
120 assigned-clock-rates = <786432000>, <49152000>, <24576000>;
121 };
122};
123
124&iomuxc {
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_hog>;
127
128 imx8qm-qmx8 {
129
130 pinctrl_hog: hoggrp{
131 fsl,pins = <
132 SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 0x00000021
133 SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021
134 SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 0x00000021
135 SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021
136 SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021
137 SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31 0x00000021
138 SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021
139 SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00 0x00000021
140 SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021
141 >;
142 };
143
144 pinctrl_fec1: fec1grp {
145 fsl,pins = <
146 SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
147 SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
148 SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
149 SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
150 SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
151 SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
152 SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
153 SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
154 SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
155 SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
156 SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
157 SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
158 SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
159 SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
160 >;
161 };
162
163 pinctrl_lpi2c0: lpi2c0grp {
164 fsl,pins = <
165 SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c
166 SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c
167 >;
168 };
169
170 pinctrl_lpi2c1: lpi2c1grp {
171 fsl,pins = <
172 SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c
173 SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c
174 >;
175 };
176
177 pinctrl_lpuart0: lpuart0grp {
178 fsl,pins = <
179 SC_P_UART0_RX_DMA_UART0_RX 0x06000020
180 SC_P_UART0_TX_DMA_UART0_TX 0x06000020
181 >;
182 };
183
184 pinctrl_lpuart1: lpuart1grp {
185 fsl,pins = <
186 SC_P_UART1_RX_DMA_UART1_RX 0x06000020
187 SC_P_UART1_TX_DMA_UART1_TX 0x06000020
188 SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020
189 SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020
190 >;
191 };
192
193 pinctrl_lpuart3: lpuart3grp {
194 fsl,pins = <
195 SC_P_M41_GPIO0_00_DMA_UART3_RX 0x06000020
196 SC_P_M41_GPIO0_01_DMA_UART3_TX 0x06000020
197 >;
198 };
199
200 pinctrl_mlb: mlbgrp {
201 fsl,pins = <
202 SC_P_MLB_SIG_CONN_MLB_SIG 0x21
203 SC_P_MLB_CLK_CONN_MLB_CLK 0x21
204 SC_P_MLB_DATA_CONN_MLB_DATA 0x21
205 >;
206 };
207
208 pinctrl_isl29023: isl29023grp {
209 fsl,pins = <
210 SC_P_ADC_IN2_LSIO_GPIO3_IO20 0x00000021
211 >;
212 };
213
214 pinctrl_usdhc1: usdhc1grp {
215 fsl,pins = <
216 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
217 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
218 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
219 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
220 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
221 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
222 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
223 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
224 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
225 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
226 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
227 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
228 >;
229 };
230
231 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
232 fsl,pins = <
233 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
234 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
235 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
236 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
237 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
238 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
239 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
240 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
241 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
242 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
243 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
244 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
245 >;
246 };
247
248 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
249 fsl,pins = <
250 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
251 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
252 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
253 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
254 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
255 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
256 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
257 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
258 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
259 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
260 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
261 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
262 >;
263 };
264
265 pinctrl_usdhc2_gpio: usdhc2grpgpio {
266 fsl,pins = <
267 SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
268 SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
269 SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
270 >;
271 };
272
273 pinctrl_usdhc2: usdhc2grp {
274 fsl,pins = <
275 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
276 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
277 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
278 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
279 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
280 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
281 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
282 >;
283 };
284
285 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
286 fsl,pins = <
287 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
288 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
289 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
290 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
291 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
292 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
293 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
294 >;
295 };
296
297 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
298 fsl,pins = <
299 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
300 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
301 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
302 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
303 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
304 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
305 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
306 >;
307 };
308
309 pinctrl_usdhc3_gpio: usdhc3grpgpio {
310 fsl,pins = <
311 SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x00000021
312 SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021
313 >;
314 };
315
316 pinctrl_usdhc3: usdhc3grp {
317 fsl,pins = <
318 SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
319 SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
320 SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
321 SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
322 SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
323 SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
324 SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021
325 >;
326 };
327
328 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
329 fsl,pins = <
330 SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
331 SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
332 SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
333 SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
334 SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
335 SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
336 SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
337 >;
338 };
339
340 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
341 fsl,pins = <
342 SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
343 SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
344 SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
345 SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
346 SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
347 SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
348 SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
349 >;
350 };
351 };
352};
353
354&lpuart0 { /* console */
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_lpuart0>;
357 status = "okay";
358};
359
360&lpuart1 { /* Q7 connector */
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_lpuart1>;
363 status = "okay";
364};
365
366&pd_dma_lpuart0 {
367 debug_console;
368};
369
370&usdhc1 {
371 pinctrl-names = "default", "state_100mhz", "state_200mhz";
372 pinctrl-0 = <&pinctrl_usdhc1>;
373 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
374 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
375 bus-width = <8>;
376 non-removable;
377 status = "okay";
378};
379
380&usdhc2 {
381 pinctrl-names = "default", "state_100mhz", "state_200mhz";
382 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
383 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
384 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
385 bus-width = <4>;
386 cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
387 wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
388 vmmc-supply = <&reg_usdhc2_vmmc>;
389 fsl,tuning-start-tap = <20>;
390 fsl,tuning-step= <2>;
391 status = "okay";
392};
393
394&usdhc3 {
395 pinctrl-names = "default", "state_100mhz", "state_200mhz";
396 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
397 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
398 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
399 bus-width = <4>;
400 cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
401 vmmc-supply = <&reg_usdhc3_vmmc>;
402 fsl,tuning-start-tap = <20>;
403 fsl,tuning-step= <2>;
404 status = "okay";
405};