| Green Wan | 7f33743 | 2021-05-27 06:52:07 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2020-2021 SiFive, Inc. |
| 4 | */ |
| 5 | |
| 6 | #ifndef _GPIO_SIFIVE_H |
| 7 | #define _GPIO_SIFIVE_H |
| 8 | |
| 9 | #define GPIO_INPUT_VAL 0x00 |
| 10 | #define GPIO_INPUT_EN 0x04 |
| 11 | #define GPIO_OUTPUT_EN 0x08 |
| 12 | #define GPIO_OUTPUT_VAL 0x0C |
| 13 | #define GPIO_RISE_IE 0x18 |
| 14 | #define GPIO_RISE_IP 0x1C |
| 15 | #define GPIO_FALL_IE 0x20 |
| 16 | #define GPIO_FALL_IP 0x24 |
| 17 | #define GPIO_HIGH_IE 0x28 |
| 18 | #define GPIO_HIGH_IP 0x2C |
| 19 | #define GPIO_LOW_IE 0x30 |
| 20 | #define GPIO_LOW_IP 0x34 |
| 21 | #define GPIO_OUTPUT_XOR 0x40 |
| 22 | |
| 23 | #define NR_GPIOS 16 |
| 24 | |
| 25 | enum gpio_state { |
| 26 | LOW, |
| 27 | HIGH |
| 28 | }; |
| 29 | |
| 30 | /* Details about a GPIO bank */ |
| 31 | struct sifive_gpio_plat { |
| 32 | void *base; /* address of registers in physical memory */ |
| 33 | }; |
| 34 | |
| 35 | #define SIFIVE_GENERIC_GPIO_NR(port, index) \ |
| 36 | (((port) * NR_GPIOS) + ((index) & (NR_GPIOS - 1))) |
| 37 | |
| 38 | #endif /* _GPIO_SIFIVE_H */ |