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git01.mediatek.com / filogic / uboot / 5c5e8d4600c34e645b78337d994630bd5c452b98 / . / arch / mips / dts / ar933x.dtsi
blob: c4f29324efe6598d1ca6e8f94f4303f853356e86 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Wills Wang8d8d2ed2016-03-16 16:59:59 +0800[diff] [blame]2/*
3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
Wills Wang8d8d2ed2016-03-16 16:59:59 +0800[diff] [blame]4 */
5
Wills Wang8d8d2ed2016-03-16 16:59:59 +0800[diff] [blame]6#include "skeleton.dtsi"
7
8/ {
9 compatible = "qca,ar933x";
10
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu@0 {
19 device_type = "cpu";
20 compatible = "mips,mips24Kc";
21 reg = <0>;
22 };
23 };
24
25 clocks {
26 #address-cells = <1>;
27 #size-cells = <1>;
28 ranges;
29
30 xtal: xtal {
31 #clock-cells = <0>;
32 compatible = "fixed-clock";
33 clock-output-names = "xtal";
34 };
35 };
36
37 pinctrl {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-all;
Wills Wang8d8d2ed2016-03-16 16:59:59 +0800[diff] [blame]39 compatible = "qca,ar933x-pinctrl";
40 ranges;
41 #address-cells = <1>;
42 #size-cells = <1>;
43 reg = <0x18040000 0x100>;
44 };
45
46 ahb {
47 compatible = "simple-bus";
48 ranges;
49
50 #address-cells = <1>;
51 #size-cells = <1>;
52
53 apb {
54 compatible = "simple-bus";
55 ranges;
56
57 #address-cells = <1>;
58 #size-cells = <1>;
59
Marek Vasut28f06b12016-05-06 20:10:36 +0200[diff] [blame]60 ehci0: ehci@1b000100 {
61 compatible = "generic-ehci";
62 reg = <0x1b000100 0x100>;
63
64 status = "disabled";
65 };
66
Wills Wang8d8d2ed2016-03-16 16:59:59 +0800[diff] [blame]67 uart0: uart@18020000 {
68 compatible = "qca,ar9330-uart";
69 reg = <0x18020000 0x20>;
Wills Wang8d8d2ed2016-03-16 16:59:59 +0800[diff] [blame]70
71 status = "disabled";
72 };
Marek Vasut00326b22016-05-06 20:10:38 +0200[diff] [blame]73
74 gmac0: eth@0x19000000 {
Wills Wang56f02192016-05-30 22:54:51 +0800[diff] [blame]75 compatible = "qca,ag933x-mac";
Marek Vasut00326b22016-05-06 20:10:38 +0200[diff] [blame]76 reg = <0x19000000 0x200>;
77 phy = <&phy0>;
78 phy-mode = "rmii";
79
80 status = "disabled";
81
82 mdio {
83 #address-cells = <1>;
84 #size-cells = <0>;
85 phy0: ethernet-phy@0 {
86 reg = <0>;
87 };
88 };
89 };
90
91 gmac1: eth@0x1a000000 {
Wills Wang56f02192016-05-30 22:54:51 +0800[diff] [blame]92 compatible = "qca,ag933x-mac";
Marek Vasut00326b22016-05-06 20:10:38 +0200[diff] [blame]93 reg = <0x1a000000 0x200>;
94 phy = <&phy0>;
95 phy-mode = "rgmii";
96
97 status = "disabled";
98 };
Wills Wang8d8d2ed2016-03-16 16:59:59 +0800[diff] [blame]99 };
100
101 spi0: spi@1f000000 {
102 compatible = "qca,ar7100-spi";
103 reg = <0x1f000000 0x10>;
Wills Wang8d8d2ed2016-03-16 16:59:59 +0800[diff] [blame]104
105 status = "disabled";
106
107 #address-cells = <1>;
108 #size-cells = <0>;
109 };
110 };
111};