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git01.mediatek.com / filogic / uboot / 5c458ea85f6046f404d28aa181b1e929c577d79e / . / dts / upstream / src / arm / nxp / imx / imx7-mba7.dtsi
blob: 3df6dff7734ae4d0d5766f155411e825f72f0e11 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0 OR X11
2/*
3 * Device Tree Include file for TQ-Systems MBa7 carrier board.
4 *
5 * Copyright (C) 2016 TQ-Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
7 * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
8 *
9 * Note: This file does not include nodes for all peripheral devices.
10 * As device driver coverage increases additional nodes can be added.
11 */
12
13#include <dt-bindings/input/input.h>
14#include <dt-bindings/net/ti-dp83867.h>
15
16/ {
17 aliases {
18 mmc0 = &usdhc3;
19 mmc1 = &usdhc1;
20 /delete-property/ mmc2;
21 };
22
23 beeper {
24 compatible = "gpio-beeper";
25 gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>;
26 };
27
28 chosen {
29 stdout-path = &uart6;
30 };
31
32 gpio_buttons: gpio-keys {
33 compatible = "gpio-keys";
34
35 button-0 {
36 /* #SWITCH_A */
37 label = "S11";
38 linux,code = <KEY_1>;
39 gpios = <&pca9555 13 GPIO_ACTIVE_LOW>;
40 };
41
42 button-1 {
43 /* #SWITCH_B */
44 label = "S12";
45 linux,code = <KEY_2>;
46 gpios = <&pca9555 14 GPIO_ACTIVE_LOW>;
47 };
48
49 button-2 {
50 /* #SWITCH_C */
51 label = "S13";
52 linux,code = <KEY_3>;
53 gpios = <&pca9555 15 GPIO_ACTIVE_LOW>;
54 };
55 };
56
57 gpio-leds {
58 compatible = "gpio-leds";
59
60 led1 {
61 label = "led1";
62 gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>;
63 linux,default-trigger = "default-on";
64 };
65
66 led2 {
67 label = "led2";
68 gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>;
69 linux,default-trigger = "heartbeat";
70 };
71 };
72
73 reg_sd1_vmmc: regulator-sd1-vmmc {
74 compatible = "regulator-fixed";
75 regulator-name = "VCC3V3_SD1";
76 regulator-min-microvolt = <3300000>;
77 regulator-max-microvolt = <3300000>;
78 regulator-always-on;
79 };
80
81 reg_fec1_pwdn: regulator-fec1-pwdn {
82 compatible = "regulator-fixed";
83 regulator-name = "PWDN_FEC1";
84 regulator-min-microvolt = <3300000>;
85 regulator-max-microvolt = <3300000>;
86 regulator-always-on;
87 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
88 enable-active-high;
89 };
90
91 reg_fec2_pwdn: regulator-fec2-pwdn {
92 compatible = "regulator-fixed";
93 regulator-name = "PWDN_FEC2";
94 regulator-min-microvolt = <3300000>;
95 regulator-max-microvolt = <3300000>;
96 regulator-always-on;
97 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
98 enable-active-high;
99 };
100
101 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
102 compatible = "regulator-fixed";
103 regulator-name = "VBUS_USBOTG1";
104 regulator-min-microvolt = <5000000>;
105 regulator-max-microvolt = <5000000>;
106 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
107 enable-active-high;
108 };
109
110 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
111 compatible = "regulator-fixed";
112 regulator-name = "VBUS_USBOTG2";
113 regulator-min-microvolt = <5000000>;
114 regulator-max-microvolt = <5000000>;
115 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
116 enable-active-high;
117 };
118
119 reg_mpcie_1v5: regulator-mpcie-1v5 {
120 compatible = "regulator-fixed";
121 regulator-name = "VCC1V5_MPCIE";
122 regulator-min-microvolt = <1500000>;
123 regulator-max-microvolt = <1500000>;
124 gpio = <&pca9555 12 GPIO_ACTIVE_HIGH>;
125 enable-active-high;
126 regulator-always-on;
127 };
128
129 reg_mpcie_3v3: regulator-mpcie-3v3 {
130 compatible = "regulator-fixed";
131 regulator-name = "VCC3V3_MPCIE";
132 regulator-min-microvolt = <3300000>;
133 regulator-max-microvolt = <3300000>;
134 gpio = <&pca9555 10 GPIO_ACTIVE_HIGH>;
135 enable-active-high;
136 regulator-always-on;
137 };
138
139 reg_mba_12v0: regulator-mba-12v0 {
140 compatible = "regulator-fixed";
141 regulator-name = "VCC12V0_MBA7";
142 regulator-min-microvolt = <12000000>;
143 regulator-max-microvolt = <12000000>;
144 gpio = <&pca9555 11 GPIO_ACTIVE_HIGH>;
145 enable-active-high;
146 };
147
148 reg_lvds_transmitter: regulator-lvds-transmitter {
149 compatible = "regulator-fixed";
150 regulator-name = "#SHTDN_LVDS";
151 regulator-min-microvolt = <3300000>;
152 regulator-max-microvolt = <3300000>;
153 gpio = <&pca9555 1 GPIO_ACTIVE_HIGH>;
154 enable-active-high;
155 };
156
157 reg_vref_1v8: regulator-vref-1v8 {
158 compatible = "regulator-fixed";
159 regulator-name = "VCC1V8_REF";
160 regulator-min-microvolt = <1800000>;
161 regulator-max-microvolt = <1800000>;
162 regulator-always-on;
163 vin-supply = <&sw2_reg>;
164 };
165
166 reg_audio_3v3: regulator-audio-3v3 {
167 compatible = "regulator-fixed";
168 regulator-name = "VCC3V3_AUDIO";
169 regulator-min-microvolt = <3300000>;
170 regulator-max-microvolt = <3300000>;
171 regulator-always-on;
172 };
173
174 sound {
175 compatible = "fsl,imx-audio-tlv320aic32x4";
176 model = "imx-audio-tlv320aic32x4";
177 ssi-controller = <&sai1>;
178 audio-codec = <&tlv320aic32x4>;
179 audio-routing =
180 "IN3_L", "Mic Jack",
181 "Mic Jack", "Mic Bias",
182 "IN1_L", "Line In Jack",
183 "IN1_R", "Line In Jack",
184 "Line Out Jack", "LOL",
185 "Line Out Jack", "LOR";
186 };
187};
188
189&adc1 {
190 vref-supply = <&reg_vref_1v8>;
191 status = "okay";
192};
193
194&adc2 {
195 vref-supply = <&reg_vref_1v8>;
196 status = "okay";
197};
198
199&ecspi1 {
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_ecspi1>;
202 cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>,
203 <&gpio4 2 GPIO_ACTIVE_LOW>;
204 status = "okay";
205};
206
207&ecspi2 {
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_ecspi2>;
210 status = "okay";
211};
212
213&fec1 {
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_enet1>;
216 phy-mode = "rgmii-id";
217 phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
218 phy-reset-duration = <1>;
219 phy-supply = <&reg_fec1_pwdn>;
220 phy-handle = <&ethphy1_0>;
221 fsl,magic-packet;
222 status = "okay";
223
224 mdio {
225 #address-cells = <1>;
226 #size-cells = <0>;
227
228 ethphy1_0: ethernet-phy@0 {
229 compatible = "ethernet-phy-ieee802.3-c22";
230 reg = <0>;
231 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
232 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
233 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
234 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
235 };
236 };
237};
238
239&flash0 {
240 partitions {
241 compatible = "fixed-partitions";
242 #address-cells = <1>;
243 #size-cells = <1>;
244
245 uboot@0 {
246 label = "U-Boot";
247 reg = <0x0 0xd0000>;
248 };
249
250 env1@d0000 {
251 label = "ENV1";
252 reg = <0xd0000 0x10000>;
253 };
254
255 env2@e0000 {
256 label = "ENV2";
257 reg = <0xe0000 0x10000>;
258 };
259
260 dtb@f0000 {
261 label = "DTB";
262 reg = <0xf0000 0x10000>;
263 };
264
265 linux@100000 {
266 label = "Linux";
267 reg = <0x100000 0x700000>;
268 };
269
270 rootfs@800000 {
271 label = "RootFS";
272 reg = <0x800000 0x3800000>;
273 };
274 };
275};
276
277&flexcan1 {
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_flexcan1>;
280 status = "okay";
281};
282
283&flexcan2 {
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_flexcan2>;
286 status = "okay";
287};
288
289&i2c1 {
290 lm75: temperature-sensor@49 {
291 compatible = "national,lm75";
292 reg = <0x49>;
293 };
294};
295
296&i2c2 {
297 clock-frequency = <100000>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_i2c2>;
300 status = "okay";
301
302 tlv320aic32x4: audio-codec@18 {
303 compatible = "ti,tlv320aic32x4";
304 reg = <0x18>;
305 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
306 clock-names = "mclk";
307 ldoin-supply = <&reg_audio_3v3>;
308 iov-supply = <&reg_audio_3v3>;
309 };
310
311 pca9555: gpio-expander@20 {
312 compatible = "nxp,pca9555";
313 reg = <0x20>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_pca9555>;
316 gpio-controller;
317 #gpio-cells = <2>;
318 interrupt-parent = <&gpio7>;
319 interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
320 interrupt-controller;
321 #interrupt-cells = <2>;
322 };
323};
324
325&i2c3 {
326 clock-frequency = <100000>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_i2c3>;
329 status = "okay";
330};
331
332&iomuxc {
333 pinctrl-names = "default";
334 pinctrl-0 = <&pinctrl_hog_mba7_1>;
335
336 pinctrl_ecspi1: ecspi1grp {
337 fsl,pins = <
338 MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c
339 MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74
340 MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74
341 MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74
342 MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74
343 MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74
344 >;
345 };
346
347 pinctrl_ecspi2: ecspi2grp {
348 fsl,pins = <
349 MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c
350 MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74
351 MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74
352 MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74
353 >;
354 };
355
356 pinctrl_enet1: enet1grp {
357 fsl,pins = <
358 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02
359 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00
360 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71
361 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71
362 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71
363 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71
364 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71
365 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71
366 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79
367 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79
368 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79
369 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79
370 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79
371 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79
372 /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
373 MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070
374 /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
375 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078
376 >;
377 };
378
379 pinctrl_flexcan1: flexcan1grp {
380 fsl,pins = <
381 MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a
382 MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52
383 >;
384 };
385
386 pinctrl_flexcan2: flexcan2grp {
387 fsl,pins = <
388 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a
389 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52
390 >;
391 };
392
393 pinctrl_hog_mba7_1: hogmba71grp {
394 fsl,pins = <
395 /* Limitation: WDOG2_B / WDOG2_RESET not usable */
396 MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c
397 MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074
398 /* #BOOT_EN */
399 MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010
400 >;
401 };
402
403 pinctrl_i2c2: i2c2grp {
404 fsl,pins = <
405 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078
406 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078
407 >;
408 };
409
410 pinctrl_i2c3: i2c3grp {
411 fsl,pins = <
412 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078
413 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078
414 >;
415 };
416
417 pinctrl_pca9555: pca95550grp {
418 fsl,pins = <
419 MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78
420 >;
421 };
422
423 pinctrl_sai1: sai1grp {
424 fsl,pins = <
425 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11
426 MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c
427 MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c
428 MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c
429
430 MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c
431 MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14
432 MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14
433 >;
434 };
435
436 pinctrl_uart3: uart3grp {
437 fsl,pins = <
438 MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e
439 MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76
440 MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76
441 MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e
442 >;
443 };
444
445 pinctrl_uart4: uart4grp {
446 fsl,pins = <
447 MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e
448 MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76
449 MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76
450 MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e
451 >;
452 };
453
454 pinctrl_uart5: uart5grp {
455 fsl,pins = <
456 MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e
457 MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76
458 >;
459 };
460
461 pinctrl_uart6: uart6grp {
462 fsl,pins = <
463 MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d
464 MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75
465 MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75
466 MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d
467 >;
468 };
469
470 pinctrl_uart7: uart7grp {
471 fsl,pins = <
472 MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e
473 MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76
474 MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76
475 /* Limitation: RTS is not connected */
476 MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e
477 >;
478 };
479
480 pinctrl_usdhc1_gpio: usdhc1grp_gpio {
481 fsl,pins = <
482 /* WP */
483 MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c
484 /* CD */
485 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c
486 /* VSELECT */
487 MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59
488 >;
489 };
490
491 pinctrl_usdhc1: usdhc1grp {
492 fsl,pins = <
493 MX7D_PAD_SD1_CMD__SD1_CMD 0x5e
494 MX7D_PAD_SD1_CLK__SD1_CLK 0x57
495 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e
496 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e
497 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e
498 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e
499 >;
500 };
501
502 pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
503 fsl,pins = <
504 MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
505 MX7D_PAD_SD1_CLK__SD1_CLK 0x57
506 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
507 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
508 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
509 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
510 >;
511 };
512
513 pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
514 fsl,pins = <
515 MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
516 MX7D_PAD_SD1_CLK__SD1_CLK 0x57
517 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
518 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
519 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
520 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
521 >;
522 };
523};
524
525&iomuxc_lpsr {
526 pinctrl_pwm1: pwm1grp {
527 fsl,pins = <
528 /* LCD_CONTRAST */
529 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50
530 >;
531 };
532
533 pinctrl_usbotg1: usbotg1grp {
534 fsl,pins = <
535 MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c
536 MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59
537 >;
538 };
539
540 pinctrl_wdog1: wdog1grp {
541 fsl,pins = <
542 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30
543 >;
544 };
545};
546
547&pwm1 {
548 pinctrl-names = "default";
549 pinctrl-0 = <&pinctrl_pwm1>;
550 status = "okay";
551};
552
553&sai1 {
554 pinctrl-names = "default";
555 pinctrl-0 = <&pinctrl_sai1>;
556 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
557 <&clks IMX7D_SAI1_ROOT_CLK>;
558 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
559 assigned-clock-rates = <0>, <36864000>;
560 status = "okay";
561};
562
563&uart3 {
564 pinctrl-names = "default";
565 pinctrl-0 = <&pinctrl_uart3>;
566 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
567 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
568 status = "okay";
569};
570
571&uart4 {
572 pinctrl-names = "default";
573 pinctrl-0 = <&pinctrl_uart4>;
574 assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
575 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
576 status = "okay";
577};
578
579&uart5 {
580 pinctrl-names = "default";
581 pinctrl-0 = <&pinctrl_uart5>;
582 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
583 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
584 status = "okay";
585};
586
587&uart6 {
588 pinctrl-names = "default";
589 pinctrl-0 = <&pinctrl_uart6>;
590 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
591 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
592 status = "okay";
593};
594
595&uart7 {
596 pinctrl-names = "default";
597 pinctrl-0 = <&pinctrl_uart7>;
598 assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
599 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
600 uart-has-rtscts;
601 linux,rs485-enabled-at-boot-time;
602 rs485-rts-active-low;
603 rs485-rx-during-tx;
604 status = "okay";
605};
606
607&usbh {
608 status = "okay";
609};
610
611&usbotg1 {
612 pinctrl-names = "default";
613 pinctrl-0 = <&pinctrl_usbotg1>;
614 vbus-supply = <&reg_usb_otg1_vbus>;
615 srp-disable;
616 hnp-disable;
617 adp-disable;
618 over-current-active-low;
619 dr_mode = "otg";
620 status = "okay";
621};
622
623&usdhc1 {
624 pinctrl-names = "default", "state_100mhz", "state_200mhz";
625 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
626 pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
627 pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
628 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
629 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
630 vmmc-supply = <&reg_sd1_vmmc>;
631 bus-width = <4>;
632 no-1-8-v;
633 status = "okay";
634};
635
636&wdog1 {
637 pinctrl-names = "default";
638 pinctrl-0 = <&pinctrl_wdog1>;
639 fsl,ext-reset-output;
640};