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git01.mediatek.com / filogic / uboot / 5c458ea85f6046f404d28aa181b1e929c577d79e / . / dts / upstream / src / arm / nxp / imx / imx6dl-lanmcu.dts
blob: 7c62db91173b78659372b3095a2676fec4eaea0f [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2019 Protonic Holland
4 * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
5 */
6
7/dts-v1/;
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/leds/common.h>
10#include "imx6dl.dtsi"
11
12/ {
13 model = "Van der Laan LANMCU";
14 compatible = "vdl,lanmcu", "fsl,imx6dl";
15
16 chosen {
17 stdout-path = &uart4;
18 };
19
20 clock_ksz8081: clock-ksz8081 {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <50000000>;
24 clock-output-names = "enet_ref_pad";
25 };
26
27 backlight: backlight {
28 compatible = "pwm-backlight";
29 pwms = <&pwm1 0 5000000 0>;
30 brightness-levels = <0 1000>;
31 num-interpolated-steps = <20>;
32 default-brightness-level = <19>;
33 };
34
35 display {
36 compatible = "fsl,imx-parallel-display";
37 pinctrl-0 = <&pinctrl_ipu1_disp>;
38 pinctrl-names = "default";
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 port@0 {
43 reg = <0>;
44
45 display_in: endpoint {
46 remote-endpoint = <&ipu1_di0_disp0>;
47 };
48 };
49
50 port@1 {
51 reg = <1>;
52
53 display_out: endpoint {
54 remote-endpoint = <&panel_in>;
55 };
56 };
57 };
58
59 leds {
60 compatible = "gpio-leds";
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_leds>;
63
64 led-0 {
65 label = "debug0";
66 function = LED_FUNCTION_STATUS;
67 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
68 linux,default-trigger = "heartbeat";
69 };
70 };
71
72 panel {
73 compatible = "edt,etm0700g0bdh6";
74 backlight = <&backlight>;
75
76 port {
77 panel_in: endpoint {
78 remote-endpoint = <&display_out>;
79 };
80 };
81 };
82
83 reg_otg_vbus: regulator-otg-vbus {
84 compatible = "regulator-fixed";
85 regulator-name = "otg-vbus";
86 regulator-min-microvolt = <5000000>;
87 regulator-max-microvolt = <5000000>;
88 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
89 enable-active-high;
90 };
91
92 usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq {
93 compatible = "mmc-pwrseq-simple";
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_wifi_npd>;
96 reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>;
97 };
98
99};
100
101&can1 {
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_can1>;
104 status = "okay";
105};
106
107&can2 {
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_can2>;
110 status = "okay";
111};
112
113&clks {
114 clocks = <&clock_ksz8081>;
115 clock-names = "enet_ref_pad";
116 assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
117 assigned-clock-parents = <&clock_ksz8081>;
118};
119
120&fec {
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_enet>;
123 phy-mode = "rmii";
124 phy-handle = <&rgmii_phy>;
125 status = "okay";
126
127 mdio {
128 #address-cells = <1>;
129 #size-cells = <0>;
130
131 /* Microchip KSZ8081RNA PHY */
132 rgmii_phy: ethernet-phy@0 {
133 reg = <0>;
134 interrupts-extended = <&gpio5 23 IRQ_TYPE_LEVEL_LOW>;
135 reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
136 reset-assert-us = <10000>;
137 reset-deassert-us = <300>;
138 };
139 };
140};
141
142&gpio1 {
143 gpio-line-names =
144 "", "SD1_CD", "", "", "", "", "", "",
145 "DEBUG_0", "BL_PWM", "", "", "", "", "", "",
146 "", "", "", "", "", "", "", "ENET_LED_GREEN",
147 "", "", "", "", "", "", "", "";
148};
149
150&gpio3 {
151 gpio-line-names =
152 "", "", "", "", "", "", "", "",
153 "", "", "", "", "", "", "", "",
154 "", "", "", "", "TS_INT", "USB_OTG1_OC", "USB_OTG1_PWR", "",
155 "", "", "", "", "UART2_CTS", "", "UART3_CTS", "";
156};
157
158&gpio5 {
159 gpio-line-names =
160 "", "", "", "", "", "", "", "",
161 "", "", "", "", "", "", "", "",
162 "", "", "", "", "", "", "ENET_RST", "ENET_INT",
163 "", "", "I2C1_SDA", "I2C1_SCL", "", "", "", "";
164};
165
166&gpio6 {
167 gpio-line-names =
168 "", "", "", "", "", "", "", "",
169 "", "", "WLAN_REG_ON", "", "", "", "", "",
170 "", "", "", "", "", "", "", "",
171 "", "", "", "", "", "", "", "";
172};
173
174&gpio7 {
175 gpio-line-names =
176 "", "", "", "", "", "", "", "",
177 "EMMC_RST", "", "", "", "", "", "", "",
178 "", "", "", "", "", "", "", "",
179 "", "", "", "", "", "", "", "";
180};
181
182&i2c1 {
183 clock-frequency = <100000>;
184 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_i2c1>;
186 status = "okay";
187
188 /* additional i2c devices are added automatically by the boot loader */
189};
190
191&i2c3 {
192 clock-frequency = <100000>;
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_i2c3>;
195 status = "okay";
196
197 touchscreen@38 {
198 compatible = "edt,edt-ft5406";
199 reg = <0x38>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_ts_edt>;
202 interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>;
203
204 touchscreen-size-x = <1792>;
205 touchscreen-size-y = <1024>;
206
207 touchscreen-fuzz-x = <0>;
208 touchscreen-fuzz-y = <0>;
209
210 /* Touch screen calibration */
211 threshold = <50>;
212 gain = <5>;
213 offset = <10>;
214 };
215
216 rtc@51 {
217 compatible = "nxp,pcf8563";
218 reg = <0x51>;
219 };
220};
221
222&ipu1_di0_disp0 {
223 remote-endpoint = <&display_in>;
224};
225
226&pwm1 {
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_pwm1>;
229 status = "okay";
230};
231
232&uart2 {
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_uart2>;
235 linux,rs485-enabled-at-boot-time;
236 uart-has-rtscts;
237 status = "okay";
238};
239
240&uart3 {
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_uart3>;
243 linux,rs485-enabled-at-boot-time;
244 uart-has-rtscts;
245 status = "okay";
246};
247
248&uart4 {
249 pinctrl-names = "default";
250 pinctrl-0 = <&pinctrl_uart4>;
251 status = "okay";
252};
253
254&usbotg {
255 vbus-supply = <&reg_otg_vbus>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_usbotg>;
258 phy_type = "utmi";
259 dr_mode = "host";
260 over-current-active-low;
261 status = "okay";
262};
263
264&usbphynop1 {
265 status = "disabled";
266};
267
268&usbphynop2 {
269 status = "disabled";
270};
271
272&usdhc1 {
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_usdhc1>;
275 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
276 no-1-8-v;
277 disable-wp;
278 cap-sd-highspeed;
279 no-mmc;
280 no-sdio;
281 status = "okay";
282};
283
284&usdhc2 {
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_usdhc2>;
287 no-1-8-v;
288 non-removable;
289 mmc-pwrseq = <&usdhc2_wifi_pwrseq>;
290 #address-cells = <1>;
291 #size-cells = <0>;
292 status = "okay";
293
294 wifi@1 {
295 reg = <1>;
296 compatible = "brcm,bcm4329-fmac";
297 };
298};
299
300&usdhc3 {
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_usdhc3>;
303 bus-width = <8>;
304 no-1-8-v;
305 non-removable;
306 no-sd;
307 no-sdio;
308 status = "okay";
309};
310
311&iomuxc {
312 pinctrl_can1: can1grp {
313 fsl,pins = <
314 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000
315 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008
316 >;
317 };
318
319 pinctrl_can2: can2grp {
320 fsl,pins = <
321 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000
322 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008
323 >;
324 };
325
326 pinctrl_enet: enetgrp {
327 fsl,pins = <
328 /* MX6QDL_ENET_PINGRP4 */
329 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
330 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
331 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
332 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
333 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
334 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
335 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
336 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
337 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
338
339 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0
340 /* Phy reset */
341 MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0
342 /* nINTRP */
343 MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0
344 >;
345 };
346
347 pinctrl_i2c1: i2c1grp {
348 fsl,pins = <
349 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1
350 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1
351 >;
352 };
353
354 pinctrl_i2c3: i2c3grp {
355 fsl,pins = <
356 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
357 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
358 >;
359 };
360
361 pinctrl_ipu1_disp: ipudisp1grp {
362 fsl,pins = <
363 /* DSE 0x30 => 25 Ohm, 0x20 => 37 Ohm, 0x10 => 75 Ohm */
364 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x30
365 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x30
366 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x30
367 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x30
368 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x30
369 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x30
370 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x30
371 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x30
372 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x30
373 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x30
374 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x30
375 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x30
376 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x30
377 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x30
378 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x30
379 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x30
380 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x30
381 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x30
382 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x30
383 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x30
384 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x30
385 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x30
386 >;
387 };
388
389 pinctrl_leds: ledsgrp {
390 fsl,pins = <
391 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
392 >;
393 };
394
395 pinctrl_pwm1: pwm1grp {
396 fsl,pins = <
397 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8
398 >;
399 };
400
401 pinctrl_ts_edt: ts1grp {
402 fsl,pins = <
403 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
404 >;
405 };
406
407 pinctrl_uart2: uart2grp {
408 fsl,pins = <
409 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
410 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
411 MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x130b1
412 >;
413 };
414
415 pinctrl_uart3: uart3grp {
416 fsl,pins = <
417 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
418 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
419 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x130b1
420 >;
421 };
422
423 pinctrl_uart4: uart4grp {
424 fsl,pins = <
425 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
426 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
427 >;
428 };
429
430 pinctrl_usbotg: usbotggrp {
431 fsl,pins = <
432 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
433 /* power enable, high active */
434 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
435 >;
436 };
437
438 pinctrl_usdhc1: usdhc1grp {
439 fsl,pins = <
440 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9
441 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
442 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
443 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
444 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
445 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
446 MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b0
447 >;
448 };
449
450 pinctrl_usdhc2: usdhc2grp {
451 fsl,pins = <
452 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
453 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
454 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
455 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
456 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
457 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
458 >;
459 };
460
461 pinctrl_usdhc3: usdhc3grp {
462 fsl,pins = <
463 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099
464 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099
465 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099
466 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099
467 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099
468 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099
469 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099
470 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099
471 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099
472 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099
473 MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
474 >;
475 };
476
477 pinctrl_wifi_npd: wifigrp {
478 fsl,pins = <
479 /* WL_REG_ON */
480 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069
481 >;
482 };
483};