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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glass509805b2015-01-27 22:13:39 -07002/*
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
Simon Glass509805b2015-01-27 22:13:39 -07004 */
5
6#include <common.h>
Bin Mengcf200302017-04-21 07:24:39 -07007#include <dm.h>
Simon Glass509805b2015-01-27 22:13:39 -07008#include <errno.h>
Bin Mengcf200302017-04-21 07:24:39 -07009#include <rtc.h>
Bin Mengacb4bf92017-04-21 07:24:31 -070010#include <asm/acpi_s3.h>
Bin Mengcf200302017-04-21 07:24:39 -070011#include <asm/cmos_layout.h>
12#include <asm/early_cmos.h>
Simon Glass509805b2015-01-27 22:13:39 -070013#include <asm/io.h>
Bin Meng07793c082015-10-11 21:37:42 -070014#include <asm/mrccache.h>
Simon Glass509805b2015-01-27 22:13:39 -070015#include <asm/post.h>
16#include <asm/processor.h>
Simon Glass6c34fc12019-09-25 08:00:11 -060017#include <asm/fsp1/fsp_support.h>
Simon Glass509805b2015-01-27 22:13:39 -070018
Simon Glassdaa93d92015-07-31 09:31:31 -060019DECLARE_GLOBAL_DATA_PTR;
20
Simon Glass295c4232017-03-28 10:27:18 -060021int arch_fsp_init(void)
Bin Mengd560c5c2015-06-07 11:33:14 +080022{
Bin Meng07793c082015-10-11 21:37:42 -070023 void *nvs;
Bin Mengcf200302017-04-21 07:24:39 -070024 int stack = CONFIG_FSP_TEMP_RAM_ADDR;
Bin Mengacb4bf92017-04-21 07:24:31 -070025 int boot_mode = BOOT_FULL_CONFIG;
26#ifdef CONFIG_HAVE_ACPI_RESUME
27 int prev_sleep_state = chipset_prev_sleep_state();
Bin Mengef61f772017-04-21 07:24:32 -070028 gd->arch.prev_sleep_state = prev_sleep_state;
Bin Mengacb4bf92017-04-21 07:24:31 -070029#endif
Bin Meng07793c082015-10-11 21:37:42 -070030
Bin Meng12440cd2015-08-20 06:40:19 -070031 if (!gd->arch.hob_list) {
Simon Glassf755a452019-09-25 08:11:27 -060032 if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE))
33 nvs = fsp_prepare_mrc_cache();
34 else
35 nvs = NULL;
Bin Mengacb4bf92017-04-21 07:24:31 -070036
37#ifdef CONFIG_HAVE_ACPI_RESUME
38 if (prev_sleep_state == ACPI_S3) {
39 if (nvs == NULL) {
40 /* If waking from S3 and no cache then */
41 debug("No MRC cache found in S3 resume path\n");
42 post_code(POST_RESUME_FAILURE);
43 /* Clear Sleep Type */
44 chipset_clear_sleep_state();
45 /* Reboot */
46 debug("Rebooting..\n");
Bin Meng6e577142018-07-19 03:07:32 -070047 outb(SYS_RST | RST_CPU, IO_PORT_RESET);
Bin Mengacb4bf92017-04-21 07:24:31 -070048 /* Should not reach here.. */
49 panic("Reboot System");
50 }
51
Bin Mengcf200302017-04-21 07:24:39 -070052 /*
Vagrant Cascadian973c0992019-05-03 14:28:37 -080053 * DM is not available yet at this point, hence call
Bin Mengcf200302017-04-21 07:24:39 -070054 * CMOS access library which does not depend on DM.
55 */
56 stack = cmos_read32(CMOS_FSP_STACK_ADDR);
Bin Mengacb4bf92017-04-21 07:24:31 -070057 boot_mode = BOOT_ON_S3_RESUME;
58 }
59#endif
Bin Meng12440cd2015-08-20 06:40:19 -070060 /*
61 * The first time we enter here, call fsp_init().
62 * Note the execution does not return to this function,
63 * instead it jumps to fsp_continue().
64 */
Bin Mengcf200302017-04-21 07:24:39 -070065 fsp_init(stack, boot_mode, nvs);
Bin Meng12440cd2015-08-20 06:40:19 -070066 } else {
67 /*
68 * The second time we enter here, adjust the size of malloc()
69 * pool before relocation. Given gd->malloc_base was adjusted
Albert ARIBAUD6cb4c462015-11-25 17:56:32 +010070 * after the call to board_init_f_init_reserve() in arch/x86/
71 * cpu/start.S, we should fix up gd->malloc_limit here.
Bin Meng12440cd2015-08-20 06:40:19 -070072 */
73 gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN;
74 }
Bin Mengd560c5c2015-06-07 11:33:14 +080075
76 return 0;
77}