blob: c1bde549ae897c9cb60e5281325de0f9b81fb5e0 [file] [log] [blame]
Nobuhiro Iwamatsu020d0412012-01-12 11:12:28 +09001/*
2 * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
3 * Copyright (C) 2011 Renesas Solutions Corp.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/io.h>
26#include <asm/processor.h>
27#include <netdev.h>
Nobuhiro Iwamatsu5c265ae2012-03-02 12:58:33 +090028#include <i2c.h>
Nobuhiro Iwamatsu020d0412012-01-12 11:12:28 +090029
30DECLARE_GLOBAL_DATA_PTR;
31
32#define MODEMR (0xFFCC0020)
33#define MODEMR_MASK (0x6)
34#define MODEMR_533MHZ (0x2)
35
36int checkboard(void)
37{
38 u32 r = readl(MODEMR);
39 if ((r & MODEMR_MASK) & MODEMR_533MHZ)
40 puts("CPU Clock: 533MHz\n");
41 else
42 puts("CPU Clock: 400MHz\n");
43
44 puts("BOARD: Renesas Technology Corp. R0P7734C00000RZ\n");
45 return 0;
46}
47
48#define MSTPSR1 (0xFFC80044)
49#define MSTPCR1 (0xFFC80034)
50#define MSTPSR1_GETHER (1 << 14)
51
52int board_init(void)
53{
54#if defined(CONFIG_SH_ETHER)
55 u32 r = readl(MSTPSR1);
56 if (r & MSTPSR1_GETHER)
57 writel((r & ~MSTPSR1_GETHER), MSTPCR1);
58#endif
Nobuhiro Iwamatsu5c265ae2012-03-02 12:58:33 +090059
60 return 0;
61}
62
63int board_late_init(void)
64{
65 u8 mac[6];
66
67 /* Read Mac Address and set*/
68 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
69 i2c_set_bus_num(CONFIG_SYS_I2C_MODULE);
70
71 /* Read MAC address */
72 i2c_read(0x50, 0x10, 0, mac, 6);
73
74 if (is_valid_ether_addr(mac))
75 eth_setenv_enetaddr("ethaddr", mac);
76
Nobuhiro Iwamatsu020d0412012-01-12 11:12:28 +090077 return 0;
78}
79
80int dram_init(void)
81{
82 gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
83 gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
84 printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
85
86 return 0;
87}
88
89#ifdef CONFIG_SMC911X
90int board_eth_init(bd_t *bis)
91{
92 int rc = 0;
93 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
94 return rc;
95}
96#endif