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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
TsiChung Liewf6afe722007-06-18 13:50:13 -05002/*
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
Alison Wang35d23df2012-03-26 21:49:05 +00006 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
TsiChung Liewf6afe722007-06-18 13:50:13 -05007 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChung Liewf6afe722007-06-18 13:50:13 -05008 */
9
TsiChung Liewf6afe722007-06-18 13:50:13 -050010#include <config.h>
TsiChungLiew16723332007-07-05 22:54:42 -050011#include <common.h>
Simon Glass0ffd9db2019-12-28 10:45:06 -070012#include <init.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060013#include <asm/global_data.h>
TsiChungLiew16723332007-07-05 22:54:42 -050014#include <asm/immap.h>
Alison Wang35d23df2012-03-26 21:49:05 +000015#include <asm/io.h>
Simon Glassdbd79542020-05-10 11:40:11 -060016#include <linux/delay.h>
TsiChung Liewf6afe722007-06-18 13:50:13 -050017
18DECLARE_GLOBAL_DATA_PTR;
19
20int checkboard(void)
21{
22 puts("Board: ");
23 puts("Freescale FireEngine 5329 EVB\n");
24 return 0;
25};
26
Simon Glassd35f3382017-04-06 12:47:05 -060027int dram_init(void)
TsiChung Liewf6afe722007-06-18 13:50:13 -050028{
Alison Wang35d23df2012-03-26 21:49:05 +000029 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
TsiChung Liewf6afe722007-06-18 13:50:13 -050030 u32 dramsize, i;
31
Tom Rinibb4dd962022-11-16 13:10:37 -050032 dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
TsiChung Liewf6afe722007-06-18 13:50:13 -050033
34 for (i = 0x13; i < 0x20; i++) {
35 if (dramsize == (1 << i))
36 break;
37 }
38 i--;
39
Tom Rinibb4dd962022-11-16 13:10:37 -050040 out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
41 out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
42 out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
TsiChung Liewf6afe722007-06-18 13:50:13 -050043
44 /* Issue PALL */
Tom Rinibb4dd962022-11-16 13:10:37 -050045 out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
TsiChung Liewf6afe722007-06-18 13:50:13 -050046
47 /* Issue LEMR */
Tom Rinibb4dd962022-11-16 13:10:37 -050048 out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
49 out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000);
TsiChung Liewf6afe722007-06-18 13:50:13 -050050
51 udelay(500);
52
53 /* Issue PALL */
Tom Rinibb4dd962022-11-16 13:10:37 -050054 out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
TsiChung Liewf6afe722007-06-18 13:50:13 -050055
56 /* Perform two refresh cycles */
Tom Rinibb4dd962022-11-16 13:10:37 -050057 out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
58 out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
TsiChung Liewf6afe722007-06-18 13:50:13 -050059
Tom Rinibb4dd962022-11-16 13:10:37 -050060 out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
TsiChung Liewf6afe722007-06-18 13:50:13 -050061
Alison Wang35d23df2012-03-26 21:49:05 +000062 out_be32(&sdram->ctrl,
Tom Rinibb4dd962022-11-16 13:10:37 -050063 (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
TsiChung Liewf6afe722007-06-18 13:50:13 -050064
65 udelay(100);
66
Simon Glass39f90ba2017-03-31 08:40:25 -060067 gd->ram_size = dramsize;
68
69 return 0;
TsiChung Liewf6afe722007-06-18 13:50:13 -050070};
71
72int testdram(void)
73{
74 /* TODO: XXX XXX XXX */
75 printf("DRAM test not implemented!\n");
76
77 return (0);
78}