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git01.mediatek.com / filogic / uboot / 5c0c3809ccc7468c4ebe219465d8d5284cc8c3e8 / . / arch / arm / dts / imx8mp-dhcom-u-boot.dtsi
blob: b05be57e71b859a22eaeda740ee99ccca1c19146 [file] [log] [blame]
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
4 */
5
6#include "imx8mp-u-boot.dtsi"
7
8/ {
9 aliases {
10 eeprom0 = &eeprom0;
11 eeprom1 = &eeprom1;
12 mmc0 = &usdhc2; /* MicroSD */
13 mmc1 = &usdhc3; /* eMMC */
14 mmc2 = &usdhc1; /* SDIO */
15 };
16
17 config {
18 dh,ram-coding-gpios = <&gpio3 22 0>, <&gpio3 23 0>, <&gpio3 24 0>;
19 };
20
21 wdt-reboot {
22 compatible = "wdt-reboot";
23 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]24 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]25 };
26};
27
28&buck4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]29 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]30};
31
32&buck5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]34};
35
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]36&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]38};
39
40&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]42};
43
44&gpio3 {
Marek Vasutc916b282023-10-16 00:41:14 +0200[diff] [blame]45 bootph-all;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]47};
48
49&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]50 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]51};
52
53&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]55};
56
57&i2c3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]59};
60
61&pinctrl_i2c3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]63};
64
65&pinctrl_i2c3_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]66 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]67};
68
69&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]71};
72
73&pinctrl_uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]74 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]75};
76
77&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]78 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]79};
80
81&pinctrl_usdhc2_100mhz {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]82 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]83};
84
85&pinctrl_usdhc2_200mhz {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]86 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]87};
88
89&pinctrl_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]90 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]91};
92
93&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]94 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]95};
96
97&pinctrl_usdhc3_100mhz {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]98 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]99};
100
101&pinctrl_usdhc3_100mhz {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]102 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]103};
104
105&pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]106 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]107
108 regulators {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]110 };
111};
112
113&reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]114 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]115};
116
117&uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]118 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]119};
120
121/* SDIO WiFi */
122&usdhc1 {
123 status = "disabled";
124};
125
126&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]127 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]128};
129
130&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]131 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]132};
133
134&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]135 bootph-pre-ram;
Marek Vasutf98c55f2022-08-12 22:41:53 +0200[diff] [blame]136};
Marek Vasut5ca41212023-09-21 20:44:17 +0200[diff] [blame]137
138&binman {
139 itb {
140 fit {
141 images {
142 fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast {
143 description = "imx8mp-dhcom-som-overlay-eth1xfast";
144 type = "flat_dt";
145 compression = "none";
146
147 blob-ext {
148 filename = "imx8mp-dhcom-som-overlay-eth1xfast.dtbo";
149 };
150 };
151
152 fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast {
153 description = "imx8mp-dhcom-som-overlay-eth2xfast";
154 type = "flat_dt";
155 compression = "none";
156
157 blob-ext {
158 filename = "imx8mp-dhcom-som-overlay-eth2xfast.dtbo";
159 };
160 };
161
162 fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast {
163 description = "imx8mp-dhcom-pdk-overlay-eth2xfast";
164 type = "flat_dt";
165 compression = "none";
166
167 blob-ext {
168 filename = "imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo";
169 };
170 };
Marek Vasut792cb562023-09-21 20:44:18 +0200[diff] [blame]171
172 fdt-dto-imx8mp-dhcom-som-overlay-rev100 {
173 description = "imx8mp-dhcom-som-overlay-rev100";
174 type = "flat_dt";
175 compression = "none";
176
177 blob-ext {
178 filename = "imx8mp-dhcom-som-overlay-rev100.dtbo";
179 };
180 };
181
Marek Vasuteaee3032023-09-21 20:44:20 +0200[diff] [blame]182 fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100 {
183 description = "imx8mp-dhcom-pdk3-overlay-rev100";
Marek Vasut792cb562023-09-21 20:44:18 +0200[diff] [blame]184 type = "flat_dt";
185 compression = "none";
186
187 blob-ext {
Marek Vasuteaee3032023-09-21 20:44:20 +0200[diff] [blame]188 filename = "imx8mp-dhcom-pdk3-overlay-rev100.dtbo";
Marek Vasut792cb562023-09-21 20:44:18 +0200[diff] [blame]189 };
190 };
Marek Vasut5ca41212023-09-21 20:44:17 +0200[diff] [blame]191 };
192
193 configurations {
194 default = "@config-DEFAULT-SEQ";
195
196 @config-SEQ {
197 fdt = "fdt-1",
198 "fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast",
199 "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast",
Marek Vasut792cb562023-09-21 20:44:18 +0200[diff] [blame]200 "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast",
201 "fdt-dto-imx8mp-dhcom-som-overlay-rev100",
Marek Vasuteaee3032023-09-21 20:44:20 +0200[diff] [blame]202 "fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100";
Marek Vasut5ca41212023-09-21 20:44:17 +0200[diff] [blame]203 };
204 };
205 };
206 };
207};