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Bryan Wu97adb222014-06-24 11:45:29 +09001/*
Alexandre Courbot7f936d42015-07-09 16:33:00 +09002 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
Bryan Wu97adb222014-06-24 11:45:29 +09003 *
Tom Rinie2378802016-01-14 22:05:13 -05004 * SPDX-License-Identifier: GPL-2.0
Bryan Wu97adb222014-06-24 11:45:29 +09005 */
6
7/* Tegra vpr routines */
8
9#include <common.h>
10#include <asm/io.h>
11#include <asm/arch/tegra.h>
12#include <asm/arch/mc.h>
13
Alexandre Courbot7f936d42015-07-09 16:33:00 +090014#include <fdt_support.h>
15
16static bool _configured;
17
Alexandre Courbotf36729d2015-10-19 13:57:03 +090018void tegra_gpu_config(void)
Bryan Wu97adb222014-06-24 11:45:29 +090019{
20 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
21
22 /* Turn VPR off */
23 writel(0, &mc->mc_video_protect_size_mb);
24 writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
25 &mc->mc_video_protect_reg_ctrl);
26 /* read back to ensure the write went through */
27 readl(&mc->mc_video_protect_reg_ctrl);
Alexandre Courbot7f936d42015-07-09 16:33:00 +090028
29 debug("configured VPR\n");
30
31 _configured = true;
32}
33
Alexandre Courbot5e270dc2015-07-09 16:33:01 +090034#if defined(CONFIG_OF_LIBFDT)
35
Stephen Warrenf4949cd2016-04-12 11:17:39 -060036int tegra_gpu_enable_node(void *blob, const char *compat)
Alexandre Courbot5e270dc2015-07-09 16:33:01 +090037{
38 int offset;
39
Stephen Warrenf4949cd2016-04-12 11:17:39 -060040 if (!_configured)
41 return 0;
42
43 offset = fdt_node_offset_by_compatible(blob, -1, compat);
44 while (offset != -FDT_ERR_NOTFOUND) {
45 fdt_status_okay(blob, offset);
46 offset = fdt_node_offset_by_compatible(blob, offset, compat);
Alexandre Courbot5e270dc2015-07-09 16:33:01 +090047 }
48
49 return 0;
50}
51
52#endif