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Marek Vasutc140e982011-11-08 23:18:08 +00001/*
Otavio Salvador90818622013-01-19 16:02:49 +00002 * Freescale i.MX23/i.MX28 Clock
Marek Vasutc140e982011-11-08 23:18:08 +00003 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Marek Vasutc140e982011-11-08 23:18:08 +00008 */
9
10#ifndef __CLOCK_H__
11#define __CLOCK_H__
12
13enum mxc_clock {
14 MXC_ARM_CLK = 0,
15 MXC_AHB_CLK,
16 MXC_IPG_CLK,
17 MXC_EMI_CLK,
18 MXC_GPMI_CLK,
19 MXC_IO0_CLK,
20 MXC_IO1_CLK,
Otavio Salvador90818622013-01-19 16:02:49 +000021 MXC_XTAL_CLK,
Marek Vasutc140e982011-11-08 23:18:08 +000022 MXC_SSP0_CLK,
Otavio Salvador90818622013-01-19 16:02:49 +000023#ifdef CONFIG_MX28
Marek Vasutc140e982011-11-08 23:18:08 +000024 MXC_SSP1_CLK,
25 MXC_SSP2_CLK,
26 MXC_SSP3_CLK,
Otavio Salvador90818622013-01-19 16:02:49 +000027#endif
Marek Vasutc140e982011-11-08 23:18:08 +000028};
29
30enum mxs_ioclock {
31 MXC_IOCLK0 = 0,
32 MXC_IOCLK1,
33};
34
35enum mxs_sspclock {
36 MXC_SSPCLK0 = 0,
Otavio Salvador90818622013-01-19 16:02:49 +000037#ifdef CONFIG_MX28
Marek Vasutc140e982011-11-08 23:18:08 +000038 MXC_SSPCLK1,
39 MXC_SSPCLK2,
40 MXC_SSPCLK3,
Otavio Salvador90818622013-01-19 16:02:49 +000041#endif
Marek Vasutc140e982011-11-08 23:18:08 +000042};
43
44uint32_t mxc_get_clock(enum mxc_clock clk);
45
Otavio Salvador2906f942013-01-11 03:19:03 +000046void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq);
47void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
48void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq);
Peng Fan93320422015-10-29 15:54:39 +080049void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq);
Marek Vasutc140e982011-11-08 23:18:08 +000050
51/* Compatibility with the FEC Ethernet driver */
52#define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK)
53
54#endif /* __CLOCK_H__ */