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git01.mediatek.com / filogic / uboot / 5bf651ee130924f04fe971394c08674c2f12cdfb / . / arch / arm / dts / imx8mm-venice-gw700x.dtsi
blob: cc850e7dce3e7de97a58582bc82bdf7f8610601d [file] [log] [blame]
Tim Harvey5fe2ef02021-03-02 14:00:20 -0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2020 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/net/ti-dp83867.h>
9
10/ {
11 memory@40000000 {
12 device_type = "memory";
13 reg = <0x0 0x40000000 0 0x80000000>;
14 };
15
16 gpio-keys {
17 compatible = "gpio-keys";
18
19 user-pb {
20 label = "user_pb";
21 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
22 linux,code = <BTN_0>;
23 };
24
25 user-pb1x {
26 label = "user_pb1x";
27 linux,code = <BTN_1>;
28 interrupt-parent = <&gsc>;
29 interrupts = <0>;
30 };
31
32 key-erased {
33 label = "key_erased";
34 linux,code = <BTN_2>;
35 interrupt-parent = <&gsc>;
36 interrupts = <1>;
37 };
38
39 eeprom-wp {
40 label = "eeprom_wp";
41 linux,code = <BTN_3>;
42 interrupt-parent = <&gsc>;
43 interrupts = <2>;
44 };
45
46 tamper {
47 label = "tamper";
48 linux,code = <BTN_4>;
49 interrupt-parent = <&gsc>;
50 interrupts = <5>;
51 };
52
53 switch-hold {
54 label = "switch_hold";
55 linux,code = <BTN_5>;
56 interrupt-parent = <&gsc>;
57 interrupts = <7>;
58 };
59 };
60};
61
62&A53_0 {
63 cpu-supply = <&buck3_reg>;
64};
65
66&A53_1 {
67 cpu-supply = <&buck3_reg>;
68};
69
70&A53_2 {
71 cpu-supply = <&buck3_reg>;
72};
73
74&A53_3 {
75 cpu-supply = <&buck3_reg>;
76};
77
78&ddrc {
79 operating-points-v2 = <&ddrc_opp_table>;
80
81 ddrc_opp_table: opp-table {
82 compatible = "operating-points-v2";
83
84 opp-25M {
85 opp-hz = /bits/ 64 <25000000>;
86 };
87
88 opp-100M {
89 opp-hz = /bits/ 64 <100000000>;
90 };
91
92 opp-750M {
93 opp-hz = /bits/ 64 <750000000>;
94 };
95 };
96};
97
98&fec1 {
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_fec1>;
101 phy-mode = "rgmii-id";
102 phy-handle = <&ethphy0>;
103 status = "okay";
104
105 mdio {
106 #address-cells = <1>;
107 #size-cells = <0>;
108
109 ethphy0: ethernet-phy@0 {
110 compatible = "ethernet-phy-ieee802.3-c22";
111 reg = <0>;
112 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
113 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
Tim Harveyba7dac32021-07-27 15:19:35 -0700[diff] [blame]114 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
Tim Harvey5fe2ef02021-03-02 14:00:20 -0800[diff] [blame]115 };
116 };
117};
118
119&i2c1 {
120 clock-frequency = <100000>;
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_i2c1>;
123 status = "okay";
124
125 gsc: gsc@20 {
126 compatible = "gw,gsc";
127 reg = <0x20>;
128 pinctrl-0 = <&pinctrl_gsc>;
129 interrupt-parent = <&gpio2>;
130 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
131 interrupt-controller;
132 #interrupt-cells = <1>;
133 #address-cells = <1>;
134 #size-cells = <0>;
135
136 adc {
137 compatible = "gw,gsc-adc";
138 #address-cells = <1>;
139 #size-cells = <0>;
140
141 channel@6 {
142 gw,mode = <0>;
143 reg = <0x06>;
144 label = "temp";
145 };
146
147 channel@8 {
148 gw,mode = <1>;
149 reg = <0x08>;
150 label = "vdd_bat";
151 };
152
153 channel@16 {
154 gw,mode = <4>;
155 reg = <0x16>;
156 label = "fan_tach";
157 };
158
159 channel@82 {
160 gw,mode = <2>;
161 reg = <0x82>;
162 label = "vdd_vin";
163 gw,voltage-divider-ohms = <22100 1000>;
164 };
165
166 channel@84 {
167 gw,mode = <2>;
168 reg = <0x84>;
169 label = "vdd_adc1";
170 gw,voltage-divider-ohms = <10000 10000>;
171 };
172
173 channel@86 {
174 gw,mode = <2>;
175 reg = <0x86>;
176 label = "vdd_adc2";
177 gw,voltage-divider-ohms = <10000 10000>;
178 };
179
180 channel@88 {
181 gw,mode = <2>;
182 reg = <0x88>;
183 label = "vdd_dram";
184 };
185
186 channel@8c {
187 gw,mode = <2>;
188 reg = <0x8c>;
189 label = "vdd_1p2";
190 };
191
192 channel@8e {
193 gw,mode = <2>;
194 reg = <0x8e>;
195 label = "vdd_1p0";
196 };
197
198 channel@90 {
199 gw,mode = <2>;
200 reg = <0x90>;
201 label = "vdd_2p5";
202 gw,voltage-divider-ohms = <10000 10000>;
203 };
204
205 channel@92 {
206 gw,mode = <2>;
207 reg = <0x92>;
208 label = "vdd_3p3";
209 gw,voltage-divider-ohms = <10000 10000>;
210 };
211
212 channel@98 {
213 gw,mode = <2>;
214 reg = <0x98>;
215 label = "vdd_0p95";
216 };
217
218 channel@9a {
219 gw,mode = <2>;
220 reg = <0x9a>;
221 label = "vdd_1p8";
222 };
223
224 channel@a2 {
225 gw,mode = <2>;
226 reg = <0xa2>;
227 label = "vdd_gsc";
228 gw,voltage-divider-ohms = <10000 10000>;
229 };
230 };
231
232 fan-controller@0 {
233 #address-cells = <1>;
234 #size-cells = <0>;
235 compatible = "gw,gsc-fan";
236 reg = <0x0a>;
237 };
238 };
239
240 gpio: gpio@23 {
241 compatible = "nxp,pca9555";
242 reg = <0x23>;
243 gpio-controller;
244 #gpio-cells = <2>;
245 interrupt-parent = <&gsc>;
246 interrupts = <4>;
247 };
248
249 eeprom@50 {
250 compatible = "atmel,24c02";
251 reg = <0x50>;
252 pagesize = <16>;
253 };
254
255 eeprom@51 {
256 compatible = "atmel,24c02";
257 reg = <0x51>;
258 pagesize = <16>;
259 };
260
261 eeprom@52 {
262 compatible = "atmel,24c02";
263 reg = <0x52>;
264 pagesize = <16>;
265 };
266
267 eeprom@53 {
268 compatible = "atmel,24c02";
269 reg = <0x53>;
270 pagesize = <16>;
271 };
272
273 rtc@68 {
274 compatible = "dallas,ds1672";
275 reg = <0x68>;
276 };
277
278 pmic@69 {
279 compatible = "mps,mp5416";
280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_pmic>;
282 reg = <0x69>;
283
284 regulators {
285 buck1 {
286 regulator-name = "vdd_0p95";
287 regulator-min-microvolt = <805000>;
288 regulator-max-microvolt = <1000000>;
289 regulator-max-microamp = <2500000>;
290 regulator-boot-on;
291 };
292
293 buck2 {
294 regulator-name = "vdd_soc";
295 regulator-min-microvolt = <805000>;
296 regulator-max-microvolt = <900000>;
297 regulator-max-microamp = <1000000>;
298 regulator-boot-on;
299 };
300
301 buck3_reg: buck3 {
302 regulator-name = "vdd_arm";
303 regulator-min-microvolt = <805000>;
304 regulator-max-microvolt = <1000000>;
305 regulator-max-microamp = <2200000>;
306 regulator-boot-on;
307 };
308
309 buck4 {
310 regulator-name = "vdd_1p8";
311 regulator-min-microvolt = <1800000>;
312 regulator-max-microvolt = <1800000>;
313 regulator-max-microamp = <500000>;
314 regulator-boot-on;
315 };
316
317 ldo1 {
318 regulator-name = "nvcc_snvs_1p8";
319 regulator-min-microvolt = <1800000>;
320 regulator-max-microvolt = <1800000>;
321 regulator-max-microamp = <300000>;
322 regulator-boot-on;
323 };
324
325 ldo2 {
326 regulator-name = "vdd_snvs_0p8";
327 regulator-min-microvolt = <800000>;
328 regulator-max-microvolt = <800000>;
329 regulator-boot-on;
330 };
331
332 ldo3 {
333 regulator-name = "vdd_0p95";
334 regulator-min-microvolt = <800000>;
335 regulator-max-microvolt = <800000>;
336 regulator-boot-on;
337 };
338
339 ldo4 {
340 regulator-name = "vdd_1p8";
341 regulator-min-microvolt = <1800000>;
342 regulator-max-microvolt = <1800000>;
343 regulator-boot-on;
344 };
345 };
346 };
347};
348
349&i2c2 {
350 clock-frequency = <400000>;
351 pinctrl-names = "default";
352 pinctrl-0 = <&pinctrl_i2c2>;
353 status = "okay";
354
355 eeprom@52 {
356 compatible = "atmel,24c32";
357 reg = <0x52>;
358 pagesize = <32>;
359 };
360};
361
362/* console */
363&uart2 {
364 pinctrl-names = "default";
365 pinctrl-0 = <&pinctrl_uart2>;
366 status = "okay";
367};
368
369/* eMMC */
370&usdhc3 {
371 pinctrl-names = "default", "state_100mhz", "state_200mhz";
372 pinctrl-0 = <&pinctrl_usdhc3>;
373 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
374 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
375 bus-width = <8>;
376 non-removable;
377 status = "okay";
378};
379
380&wdog1 {
381 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_wdog>;
383 fsl,ext-reset-output;
384 status = "okay";
385};
386
387&iomuxc {
388 pinctrl_fec1: fec1grp {
389 fsl,pins = <
390 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
391 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
392 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
393 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
394 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
395 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
396 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
397 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
398 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
399 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
400 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
401 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
402 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
403 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
404 MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19
405 >;
406 };
407
408 pinctrl_gsc: gscgrp {
409 fsl,pins = <
410 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x159
411 >;
412 };
413
414 pinctrl_i2c1: i2c1grp {
415 fsl,pins = <
416 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
417 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
418 >;
419 };
420
421 pinctrl_i2c2: i2c2grp {
422 fsl,pins = <
423 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
424 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
425 >;
426 };
427
428 pinctrl_pmic: pmicgrp {
429 fsl,pins = <
430 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
431 >;
432 };
433
434 pinctrl_uart2: uart2grp {
435 fsl,pins = <
436 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
437 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
438 >;
439 };
440
441 pinctrl_usdhc3: usdhc3grp {
442 fsl,pins = <
443 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
444 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
445 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
446 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
447 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
448 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
449 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
450 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
451 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
452 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
453 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
454 >;
455 };
456
457 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
458 fsl,pins = <
459 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
460 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
461 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
462 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
463 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
464 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
465 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
466 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
467 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
468 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
469 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
470 >;
471 };
472
473 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
474 fsl,pins = <
475 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
476 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
477 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
478 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
479 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
480 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
481 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
482 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
483 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
484 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
485 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
486 >;
487 };
488
489 pinctrl_wdog: wdoggrp {
490 fsl,pins = <
491 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
492 >;
493 };
494};