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Ilya Yanok016b7022009-08-11 02:32:09 +04001/*
2 * Copyright (C) 2007 Sascha Hauer, Pengutronix
3 * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
4 * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 *
21 */
22
23#include <common.h>
24#include <asm/io.h>
25#include <asm/arch/imx-regs.h>
26
27DECLARE_GLOBAL_DATA_PTR;
28
Fabio Estevamf231efb2011-10-13 05:34:59 +000029int board_init(void)
Ilya Yanok016b7022009-08-11 02:32:09 +040030{
31 struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
Heiko Schocherc8f51122010-03-05 07:36:33 +010032#if defined(CONFIG_SYS_NAND_LARGEPAGE)
33 struct system_control_regs *sc_regs =
34 (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
35#endif
Ilya Yanok016b7022009-08-11 02:32:09 +040036
37 gd->bd->bi_arch_number = MACH_TYPE_IMX27LITE;
38 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
39
40#ifdef CONFIG_MXC_UART
Fabio Estevamaf905dd2011-07-01 07:15:52 +000041 mx27_uart1_init_pins();
Ilya Yanok016b7022009-08-11 02:32:09 +040042#endif
43#ifdef CONFIG_FEC_MXC
44 mx27_fec_init_pins();
45 imx_gpio_mode((GPIO_PORTC | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 31));
46 writel(readl(&regs->port[PORTC].dr) | (1 << 31),
47 &regs->port[PORTC].dr);
48#endif
49#ifdef CONFIG_MXC_MMC
Heiko Schocherc8f51122010-03-05 07:36:33 +010050#if defined(CONFIG_MAGNESIUM)
51 mx27_sd1_init_pins();
52#else
Ilya Yanok016b7022009-08-11 02:32:09 +040053 mx27_sd2_init_pins();
54#endif
Heiko Schocherc8f51122010-03-05 07:36:33 +010055#endif
Ilya Yanok016b7022009-08-11 02:32:09 +040056
Heiko Schocherc8f51122010-03-05 07:36:33 +010057#if defined(CONFIG_SYS_NAND_LARGEPAGE)
58 /*
59 * set in FMCR NF_FMS Bit(5) to 1
60 * (NAND Flash with 2 Kbyte page size)
61 */
62 writel(readl(&sc_regs->fmcr) | (1 << 5), &sc_regs->fmcr);
63#endif
Ilya Yanok016b7022009-08-11 02:32:09 +040064 return 0;
65}
66
Fabio Estevamf231efb2011-10-13 05:34:59 +000067int dram_init(void)
Ilya Yanok016b7022009-08-11 02:32:09 +040068{
Heiko Schocher0e2412a2010-09-17 13:10:42 +020069 /* dram_init must store complete ramsize in gd->ram_size */
Albert ARIBAUDa9606732011-07-03 05:55:33 +000070 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
Heiko Schocher0e2412a2010-09-17 13:10:42 +020071 PHYS_SDRAM_1_SIZE);
72 return 0;
73}
Ilya Yanok016b7022009-08-11 02:32:09 +040074
Heiko Schocher0e2412a2010-09-17 13:10:42 +020075void dram_init_banksize(void)
76{
77 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
Albert ARIBAUDa9606732011-07-03 05:55:33 +000078 gd->bd->bi_dram[0].size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
Ilya Yanok016b7022009-08-11 02:32:09 +040079 PHYS_SDRAM_1_SIZE);
Ilya Yanok016b7022009-08-11 02:32:09 +040080#if CONFIG_NR_DRAM_BANKS > 1
81 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
Albert ARIBAUDa9606732011-07-03 05:55:33 +000082 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
Ilya Yanok016b7022009-08-11 02:32:09 +040083 PHYS_SDRAM_2_SIZE);
84#endif
Ilya Yanok016b7022009-08-11 02:32:09 +040085}
86
87int checkboard(void)
88{
Fabio Estevamf231efb2011-10-13 05:34:59 +000089 puts("Board: ");
Heiko Schocherc8f51122010-03-05 07:36:33 +010090 puts(CONFIG_BOARDNAME);
Ilya Yanok016b7022009-08-11 02:32:09 +040091 return 0;
92}