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Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +09001/*
2 * include/configs/lager.h
3 * This file is lager board configuration.
4 *
Nobuhiro Iwamatsub6169ac2014-11-10 14:34:07 +09005 * Copyright (C) 2013, 2014 Renesas Electronics Corporation
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +09006 *
7 * SPDX-License-Identifier: GPL-2.0
8 */
9
10#ifndef __LAGER_H
11#define __LAGER_H
12
13#undef DEBUG
Nobuhiro Iwamatsu7c112732015-10-10 05:58:28 +090014#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Lager"
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +090015
Nobuhiro Iwamatsub6169ac2014-11-10 14:34:07 +090016#include "rcar-gen2-common.h"
Nobuhiro Iwamatsue59703e2014-03-31 15:22:31 +090017
Marek Vasut016a6052018-04-23 20:24:06 +020018#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
19#define STACK_AREA_SIZE 0x00100000
20#define LOW_LEVEL_MERAM_STACK \
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +090021 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
22
23/* MEMORY */
Nobuhiro Iwamatsub6169ac2014-11-10 14:34:07 +090024#define RCAR_GEN2_SDRAM_BASE 0x40000000
25#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
26#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +090027
Nobuhiro Iwamatsu0929b742013-10-20 20:28:24 +090028/* SH Ether */
Nobuhiro Iwamatsu0929b742013-10-20 20:28:24 +090029#define CONFIG_SH_ETHER_USE_PORT 0
30#define CONFIG_SH_ETHER_PHY_ADDR 0x1
31#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
Nobuhiro Iwamatsu0929b742013-10-20 20:28:24 +090032#define CONFIG_SH_ETHER_CACHE_WRITEBACK
33#define CONFIG_SH_ETHER_CACHE_INVALIDATE
Marek Vasut016a6052018-04-23 20:24:06 +020034#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
Nobuhiro Iwamatsu0929b742013-10-20 20:28:24 +090035#define CONFIG_BITBANGMII
36#define CONFIG_BITBANGMII_MULTI
37
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +090038/* Board Clock */
Nobuhiro Iwamatsu18d337a2014-03-31 14:03:07 +090039#define RMOBILE_XTAL_CLK 20000000u
40#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
Marek Vasut016a6052018-04-23 20:24:06 +020041#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +090042
43#define CONFIG_SYS_TMU_CLK_DIV 4
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +090044
Marek Vasut016a6052018-04-23 20:24:06 +020045#define CONFIG_EXTRA_ENV_SETTINGS \
46 "fdt_high=0xffffffff\0" \
47 "initrd_high=0xffffffff\0"
Nobuhiro Iwamatsubaf336a2014-12-03 15:30:30 +090048
Marek Vasut016a6052018-04-23 20:24:06 +020049/* SPL support */
50#define CONFIG_SPL_TEXT_BASE 0xe6300000
51#define CONFIG_SPL_STACK 0xe6340000
52#define CONFIG_SPL_MAX_SIZE 0x4000
53#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
54#ifdef CONFIG_SPL_BUILD
55#define CONFIG_CONS_SCIF0
56#define CONFIG_SH_SCIF_CLK_FREQ 65000000
57#endif
Nobuhiro Iwamatsu4ca383a2014-11-21 10:19:32 +090058
Nobuhiro Iwamatsud74c8cf2013-11-21 17:06:46 +090059#endif /* __LAGER_H */