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Simon Glass07e922a2015-04-28 20:25:10 -06001/*
2 * Copyright(c) 2009 Intel Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
5 */
6
7#ifndef _LINUX_SFI_H
8#define _LINUX_SFI_H
9
10#include <errno.h>
11#include <linux/types.h>
12
13/* Table signatures reserved by the SFI specification */
14#define SFI_SIG_SYST "SYST"
15#define SFI_SIG_FREQ "FREQ"
16#define SFI_SIG_CPUS "CPUS"
17#define SFI_SIG_MTMR "MTMR"
18#define SFI_SIG_MRTC "MRTC"
19#define SFI_SIG_MMAP "MMAP"
20#define SFI_SIG_APIC "APIC"
21#define SFI_SIG_XSDT "XSDT"
22#define SFI_SIG_WAKE "WAKE"
23#define SFI_SIG_DEVS "DEVS"
24#define SFI_SIG_GPIO "GPIO"
25
26#define SFI_SIGNATURE_SIZE 4
27#define SFI_OEM_ID_SIZE 6
28#define SFI_OEM_TABLE_ID_SIZE 8
29
30#define SFI_NAME_LEN 16
31#define SFI_TABLE_MAX_ENTRIES 16
32
33#define SFI_GET_NUM_ENTRIES(ptable, entry_type) \
34 ((ptable->header.len - sizeof(struct sfi_table_header)) / \
35 (sizeof(entry_type)))
36/*
37 * Table structures must be byte-packed to match the SFI specification,
38 * as they are provided by the BIOS.
39 */
40struct __packed sfi_table_header {
41 char sig[SFI_SIGNATURE_SIZE];
42 u32 len;
43 u8 rev;
44 u8 csum;
45 char oem_id[SFI_OEM_ID_SIZE];
46 char oem_table_id[SFI_OEM_TABLE_ID_SIZE];
47};
48
49struct __packed sfi_table_simple {
50 struct sfi_table_header header;
51 u64 pentry[1];
52};
53
54/* Comply with UEFI spec 2.1 */
55struct __packed sfi_mem_entry {
56 u32 type;
57 u64 phys_start;
58 u64 virt_start;
59 u64 pages;
60 u64 attrib;
61};
62
Felipe Balbie564d592017-07-06 14:41:52 +030063/* Memory type definitions */
64enum sfi_mem_type {
65 SFI_MEM_RESERVED,
66 SFI_LOADER_CODE,
67 SFI_LOADER_DATA,
68 SFI_BOOT_SERVICE_CODE,
69 SFI_BOOT_SERVICE_DATA,
70 SFI_RUNTIME_SERVICE_CODE,
71 SFI_RUNTIME_SERVICE_DATA,
72 SFI_MEM_CONV,
73 SFI_MEM_UNUSABLE,
74 SFI_ACPI_RECLAIM,
75 SFI_ACPI_NVS,
76 SFI_MEM_MMIO,
77 SFI_MEM_IOPORT,
78 SFI_PAL_CODE,
79 SFI_MEM_TYPEMAX,
80};
81
Simon Glass07e922a2015-04-28 20:25:10 -060082struct __packed sfi_cpu_table_entry {
83 u32 apic_id;
84};
85
86struct __packed sfi_cstate_table_entry {
87 u32 hint; /* MWAIT hint */
88 u32 latency; /* latency in ms */
89};
90
91struct __packed sfi_apic_table_entry {
92 u64 phys_addr; /* phy base addr for APIC reg */
93};
94
95struct __packed sfi_freq_table_entry {
96 u32 freq_mhz; /* in MHZ */
97 u32 latency; /* transition latency in ms */
98 u32 ctrl_val; /* value to write to PERF_CTL */
99};
100
101struct __packed sfi_wake_table_entry {
102 u64 phys_addr; /* pointer to where the wake vector locates */
103};
104
105struct __packed sfi_timer_table_entry {
106 u64 phys_addr; /* phy base addr for the timer */
107 u32 freq_hz; /* in HZ */
108 u32 irq;
109};
110
111struct __packed sfi_rtc_table_entry {
112 u64 phys_addr; /* phy base addr for the RTC */
113 u32 irq;
114};
115
116struct __packed sfi_device_table_entry {
117 u8 type; /* bus type, I2C, SPI or ...*/
118 u8 host_num; /* attached to host 0, 1...*/
119 u16 addr;
120 u8 irq;
121 u32 max_freq;
122 char name[SFI_NAME_LEN];
123};
124
125enum {
126 SFI_DEV_TYPE_SPI = 0,
127 SFI_DEV_TYPE_I2C,
128 SFI_DEV_TYPE_UART,
129 SFI_DEV_TYPE_HSI,
130 SFI_DEV_TYPE_IPC,
131 SFI_DEV_TYPE_SD,
132};
133
134struct __packed sfi_gpio_table_entry {
135 char controller_name[SFI_NAME_LEN];
136 u16 pin_no;
137 char pin_name[SFI_NAME_LEN];
138};
139
140struct sfi_xsdt_header {
141 uint32_t oem_revision;
142 uint32_t creator_id;
143 uint32_t creator_revision;
144};
145
146typedef int (*sfi_table_handler) (struct sfi_table_header *table);
147
148/**
149 * write_sfi_table() - Write Simple Firmware Interface tables
150 *
151 * @base: Address to write table to
152 * @return address to use for the next table
153 */
Simon Glassca37a392017-01-16 07:03:35 -0700154ulong write_sfi_table(ulong base);
Simon Glass07e922a2015-04-28 20:25:10 -0600155
156#endif /*_LINUX_SFI_H */