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git01.mediatek.com / filogic / uboot / 5ba115901775f2cdde9a4301f1ca55ae257ae4a1 / . / arch / arm / dts / socfpga_arria10_socdk_sdmmc-u-boot.dtsi
blob: 10f8a959a0084b5db03aad3e4702873df9be9e47 [file] [log] [blame]
Ley Foon Tanff33e732020-04-07 15:43:12 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2014-2015, 2020 Intel. All rights reserved.
4 */
5
Ley Foon Tan75243a72020-07-08 16:34:01 +0800[diff] [blame]6#include "socfpga_arria10_socdk_sdmmc_handoff.h"
7#include "socfpga_arria10-handoff.dtsi"
Ley Foon Tanff33e732020-04-07 15:43:12 +0800[diff] [blame]8#include "socfpga_arria10_handoff_u-boot.dtsi"
9#include "socfpga_arria10_socdk-u-boot.dtsi"
10
11/ {
12 chosen {
13 firmware-loader = <&fs_loader0>;
14 };
15
16 fs_loader0: fs-loader {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]17 bootph-all;
Ley Foon Tanff33e732020-04-07 15:43:12 +0800[diff] [blame]18 compatible = "u-boot,fs-loader";
19 phandlepart = <&mmc 1>;
20 };
21};
22
23&fpga_mgr {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]24 bootph-all;
Ley Foon Tanff33e732020-04-07 15:43:12 +0800[diff] [blame]25 altr,bitstream = "fit_spl_fpga.itb";
26};
27
28&mmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]29 bootph-all;
Ley Foon Tanff33e732020-04-07 15:43:12 +0800[diff] [blame]30};
31
32/* Clock available early */
33&main_sdmmc_clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-all;
Ley Foon Tanff33e732020-04-07 15:43:12 +0800[diff] [blame]35};
36
37&peri_sdmmc_clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-all;
Ley Foon Tanff33e732020-04-07 15:43:12 +0800[diff] [blame]39};
40
41&sdmmc_free_clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-all;
Ley Foon Tanff33e732020-04-07 15:43:12 +0800[diff] [blame]43};
44
45&sdmmc_clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-all;
Ley Foon Tanff33e732020-04-07 15:43:12 +0800[diff] [blame]47};