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git01.mediatek.com / filogic / uboot / 5ba115901775f2cdde9a4301f1ca55ae257ae4a1 / . / arch / arm / dts / omap4460.dtsi
blob: 21ddff965c83e37c7129584647a42cae1a63f3ad [file] [log] [blame]
Andrew Davis42e1d602023-04-11 13:25:00 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
Tero Kristo9bae57e2020-06-16 11:03:05 +0300[diff] [blame]2/*
3 * Device Tree Source for OMAP4460 SoC
4 *
Andrew Davis42e1d602023-04-11 13:25:00 -0500[diff] [blame]5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
Tero Kristo9bae57e2020-06-16 11:03:05 +0300[diff] [blame]6 */
7#include "omap4.dtsi"
8
9/ {
10 cpus {
11 /* OMAP446x 'standard device' variants OPP50 to OPPTurbo */
12 cpu0: cpu@0 {
13 operating-points = <
14 /* kHz uV */
15 350000 1025000
16 700000 1200000
17 920000 1313000
18 >;
19 clock-latency = <300000>; /* From legacy driver */
20
21 /* cooling options */
22 #cooling-cells = <2>; /* min followed by max */
23 };
24 };
25
26 pmu {
27 compatible = "arm,cortex-a9-pmu";
28 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
30 ti,hwmods = "debugss";
31 };
32
33 thermal-zones {
34 #include "omap4-cpu-thermal.dtsi"
35 };
36
37 ocp {
38 bandgap: bandgap@4a002260 {
39 reg = <0x4a002260 0x4
40 0x4a00232C 0x4
41 0x4a002378 0x18>;
42 compatible = "ti,omap4460-bandgap";
43 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
44 gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* tshut */
45
46 #thermal-sensor-cells = <0>;
47 };
48
49 abb_mpu: regulator-abb-mpu {
50 status = "okay";
51
52 reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
53 <0x4A002268 0x4>;
54 reg-names = "base-address", "int-address",
55 "efuse-address";
56
57 ti,abb_info = <
58 /*uV ABB efuse rbb_m fbb_m vset_m*/
59 1025000 0 0 0 0 0
60 1200000 0 0 0 0 0
61 1313000 0 0 0x100000 0x40000 0
62 1375000 1 0 0 0 0
63 1389000 1 0 0 0 0
64 >;
65 };
66
67 abb_iva: regulator-abb-iva {
68 status = "okay";
69
70 reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>,
71 <0x4A002268 0x4>;
72 reg-names = "base-address", "int-address",
73 "efuse-address";
74
75 ti,abb_info = <
76 /*uV ABB efuse rbb_m fbb_m vset_m*/
77 950000 0 0 0 0 0
78 1140000 0 0 0 0 0
79 1291000 0 0 0x200000 0 0
80 1375000 1 0 0 0 0
81 1376000 1 0 0 0 0
82 >;
83 };
84 };
85
86};
87
88&cpu_thermal {
89 coefficients = <348 (-9301)>;
90};
91
92/* Only some L4 CFG interconnect ranges are different on 4460 */
93&l4_cfg_segment_300000 {
94 ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */
95 <0x00040000 0x00340000 0x001000>, /* ap 68 */
96 <0x00020000 0x00320000 0x004000>, /* ap 71 */
97 <0x00024000 0x00324000 0x002000>, /* ap 72 */
98 <0x00026000 0x00326000 0x001000>, /* ap 73 */
99 <0x00027000 0x00327000 0x001000>, /* ap 74 */
100 <0x00028000 0x00328000 0x001000>, /* ap 75 */
101 <0x00029000 0x00329000 0x001000>, /* ap 76 */
102 <0x00030000 0x00330000 0x010000>, /* ap 77 */
103 <0x0002a000 0x0032a000 0x002000>, /* ap 90 */
104 <0x0002c000 0x0032c000 0x004000>, /* ap 91 */
105 <0x00010000 0x00310000 0x008000>, /* ap 92 */
106 <0x00018000 0x00318000 0x004000>, /* ap 93 */
107 <0x0001c000 0x0031c000 0x002000>, /* ap 94 */
108 <0x0001e000 0x0031e000 0x002000>; /* ap 95 */
109};
110
111&l4_cfg_target_0 {
112 ranges = <0x00000000 0x00000000 0x00010000>,
113 <0x00010000 0x00010000 0x00008000>,
114 <0x00018000 0x00018000 0x00004000>,
115 <0x0001c000 0x0001c000 0x00002000>,
116 <0x0001e000 0x0001e000 0x00002000>,
117 <0x00020000 0x00020000 0x00004000>,
118 <0x00024000 0x00024000 0x00002000>,
119 <0x00026000 0x00026000 0x00001000>,
120 <0x00027000 0x00027000 0x00001000>,
121 <0x00028000 0x00028000 0x00001000>,
122 <0x00029000 0x00029000 0x00001000>,
123 <0x0002a000 0x0002a000 0x00002000>,
124 <0x0002c000 0x0002c000 0x00004000>,
125 <0x00030000 0x00030000 0x00010000>;
126};
127
128/include/ "omap446x-clocks.dtsi"