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git01.mediatek.com / filogic / uboot / 5ba115901775f2cdde9a4301f1ca55ae257ae4a1 / . / arch / arm / dts / dra72-evm.dts
blob: 2f2441204635a070f68724bad1a20ad0deb471ff [file] [log] [blame]
Andrew Davis05618992023-04-11 13:24:58 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
Tom Rinie33af1c2015-07-31 19:55:12 -0400[diff] [blame]2/*
Andrew Davis05618992023-04-11 13:24:58 -0500[diff] [blame]3 * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
Tom Rinie33af1c2015-07-31 19:55:12 -0400[diff] [blame]4 */
Lokesh Vutlada047422016-11-23 13:25:29 +0530[diff] [blame]5#include "dra72-evm-common.dtsi"
Lokesh Vutlacfa23a42017-08-21 12:50:59 +0530[diff] [blame]6#include "dra72x-mmc-iodelay.dtsi"
Tom Rinie33af1c2015-07-31 19:55:12 -0400[diff] [blame]7/ {
8 model = "TI DRA722";
Tom Rinie33af1c2015-07-31 19:55:12 -0400[diff] [blame]9
Lokesh Vutlada047422016-11-23 13:25:29 +0530[diff] [blame]10 memory@0 {
Tom Rinie33af1c2015-07-31 19:55:12 -0400[diff] [blame]11 device_type = "memory";
Lokesh Vutlada047422016-11-23 13:25:29 +0530[diff] [blame]12 reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
Tom Rinie33af1c2015-07-31 19:55:12 -0400[diff] [blame]13 };
Lokesh Vutlacfa23a42017-08-21 12:50:59 +0530[diff] [blame]14
15 evm_1v8_sw: fixedregulator-evm_1v8 {
16 compatible = "regulator-fixed";
17 regulator-name = "evm_1v8";
18 regulator-min-microvolt = <1800000>;
19 regulator-max-microvolt = <1800000>;
20 vin-supply = <&smps4_reg>;
21 regulator-always-on;
22 regulator-boot-on;
23 };
Tom Rinie33af1c2015-07-31 19:55:12 -0400[diff] [blame]24};
25
Lokesh Vutlada047422016-11-23 13:25:29 +0530[diff] [blame]26&i2c1 {
27 tps65917: tps65917@58 {
28 reg = <0x58>;
Tom Rinie33af1c2015-07-31 19:55:12 -0400[diff] [blame]29
Lokesh Vutlada047422016-11-23 13:25:29 +0530[diff] [blame]30 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
31 };
Tom Rinie33af1c2015-07-31 19:55:12 -0400[diff] [blame]32};
33
Lokesh Vutlada047422016-11-23 13:25:29 +0530[diff] [blame]34#include "dra72-evm-tps65917.dtsi"
Tom Rinie33af1c2015-07-31 19:55:12 -0400[diff] [blame]35
36&hdmi {
Tom Rinie33af1c2015-07-31 19:55:12 -0400[diff] [blame]37 vdda-supply = <&ldo3_reg>;
Mugunthan V Nb8c6b022016-09-27 13:01:41 +0530[diff] [blame]38};
Tom Rinie33af1c2015-07-31 19:55:12 -0400[diff] [blame]39
Lokesh Vutlada047422016-11-23 13:25:29 +0530[diff] [blame]40&pcf_gpio_21 {
41 interrupt-parent = <&gpio6>;
42 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
43};
44
Mugunthan V Nb8c6b022016-09-27 13:01:41 +0530[diff] [blame]45&mac {
Lokesh Vutlada047422016-11-23 13:25:29 +0530[diff] [blame]46 slaves = <1>;
47 mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
48};
49
50&cpsw_emac0 {
Grygorii Strashkocd8cbcb2019-08-31 10:30:32 +0300[diff] [blame]51 phy-handle = <&ethphy0>;
Lokesh Vutlada047422016-11-23 13:25:29 +0530[diff] [blame]52 phy-mode = "rgmii";
Tom Rinie33af1c2015-07-31 19:55:12 -0400[diff] [blame]53};
Lokesh Vutlacfa23a42017-08-21 12:50:59 +0530[diff] [blame]54
Grygorii Strashkocd8cbcb2019-08-31 10:30:32 +0300[diff] [blame]55&davinci_mdio {
56 ethphy0: ethernet-phy@3 {
57 reg = <3>;
58 };
59};
60
Lokesh Vutlacfa23a42017-08-21 12:50:59 +0530[diff] [blame]61&mmc1 {
62 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
63 pinctrl-0 = <&mmc1_pins_default>;
64 pinctrl-1 = <&mmc1_pins_hs>;
65 pinctrl-2 = <&mmc1_pins_sdr12>;
66 pinctrl-3 = <&mmc1_pins_sdr25>;
67 pinctrl-4 = <&mmc1_pins_sdr50>;
68 pinctrl-5 = <&mmc1_pins_ddr50_rev10>;
69 pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev10_conf>;
70 vqmmc-supply = <&ldo1_reg>;
71};
72
73&mmc2 {
74 pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
75 pinctrl-0 = <&mmc2_pins_default>;
76 pinctrl-1 = <&mmc2_pins_hs>;
77 pinctrl-2 = <&mmc2_pins_ddr_rev10>;
78 pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>;
79 vmmc-supply = <&evm_1v8_sw>;
80};