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Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +09001/*
Masahiro Yamada860f2f82015-02-05 14:30:21 +09002 * Copyright (C) 2012-2015 Panasonic Corporation
Masahiro Yamada37797532015-03-23 00:07:24 +09003 * Copyright (C) 2015 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +09005 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9/* U-boot - Common settings for UniPhier Family */
10
11#ifndef __CONFIG_UNIPHIER_COMMON_H__
12#define __CONFIG_UNIPHIER_COMMON_H__
13
Masahiro Yamada1e72b1c2014-12-06 00:03:22 +090014#if defined(CONFIG_MACH_PH1_PRO4)
15#define CONFIG_DDR_NUM_CH0 2
16#define CONFIG_DDR_NUM_CH1 2
17
18/* Physical start address of SDRAM */
19#define CONFIG_SDRAM0_BASE 0x80000000
20#define CONFIG_SDRAM0_SIZE 0x20000000
21#define CONFIG_SDRAM1_BASE 0xa0000000
22#define CONFIG_SDRAM1_SIZE 0x20000000
23#endif
24
25#if defined(CONFIG_MACH_PH1_LD4)
26#define CONFIG_DDR_NUM_CH0 1
27#define CONFIG_DDR_NUM_CH1 1
28
29/* Physical start address of SDRAM */
30#define CONFIG_SDRAM0_BASE 0x80000000
31#define CONFIG_SDRAM0_SIZE 0x10000000
32#define CONFIG_SDRAM1_BASE 0x90000000
33#define CONFIG_SDRAM1_SIZE 0x10000000
34#endif
35
36#if defined(CONFIG_MACH_PH1_SLD8)
37#define CONFIG_DDR_NUM_CH0 1
38#define CONFIG_DDR_NUM_CH1 1
39
40/* Physical start address of SDRAM */
41#define CONFIG_SDRAM0_BASE 0x80000000
42#define CONFIG_SDRAM0_SIZE 0x10000000
43#define CONFIG_SDRAM1_BASE 0x90000000
44#define CONFIG_SDRAM1_SIZE 0x10000000
45#endif
46
Masahiro Yamadaa8dd2012015-01-13 12:44:39 +090047#define CONFIG_I2C_EEPROM
48#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
49
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +090050/*
51 * Support card address map
52 */
53#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
54# define CONFIG_SUPPORT_CARD_BASE 0x03f00000
55# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
56# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000)
57# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000)
58#endif
59
60#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
61# define CONFIG_SUPPORT_CARD_BASE 0x08000000
62# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
63# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00401630)
64# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00200000)
65#endif
66
Masahiro Yamada50c12542014-10-23 22:26:10 +090067#ifdef CONFIG_SYS_NS16550_SERIAL
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +090068#define CONFIG_SYS_NS16550
69#define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE
70#define CONFIG_SYS_NS16550_CLK 12288000
71#define CONFIG_SYS_NS16550_REG_SIZE -2
Masahiro Yamada50c12542014-10-23 22:26:10 +090072#endif
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +090073
Masahiro Yamada1e72b1c2014-12-06 00:03:22 +090074/* TODO: move to Kconfig and device tree */
75#if 0
76#define CONFIG_SYS_NS16550_SERIAL
77#endif
78
79#define CONFIG_SMC911X
80
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +090081#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE
82#define CONFIG_SMC911X_32_BIT
83
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +090084/*-----------------------------------------------------------------------
85 * MMU and Cache Setting
86 *----------------------------------------------------------------------*/
87
88/* Comment out the following to enable L1 cache */
89/* #define CONFIG_SYS_ICACHE_OFF */
90/* #define CONFIG_SYS_DCACHE_OFF */
91
Masahiro Yamadad50f3362015-02-27 02:27:01 +090092#define CONFIG_SYS_CACHELINE_SIZE 32
93
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +090094/* Comment out the following to enable L2 cache */
95#define CONFIG_UNIPHIER_L2CACHE_ON
96
97#define CONFIG_DISPLAY_CPUINFO
98#define CONFIG_DISPLAY_BOARDINFO
Masahiro Yamada4cd15c62015-02-05 14:42:56 +090099#define CONFIG_MISC_INIT_F
Masahiro Yamada1f3d9c72015-02-05 14:42:54 +0900100#define CONFIG_BOARD_EARLY_INIT_F
Masahiro Yamada88216812014-12-06 00:03:26 +0900101#define CONFIG_BOARD_EARLY_INIT_R
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900102#define CONFIG_BOARD_LATE_INIT
103
104#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
105
106#define CONFIG_TIMESTAMP
107
108/* FLASH related */
109#define CONFIG_MTD_DEVICE
110
111/*
112 * uncomment the following to disable FLASH related code.
113 */
114/* #define CONFIG_SYS_NO_FLASH */
115
116#define CONFIG_FLASH_CFI_DRIVER
117#define CONFIG_SYS_FLASH_CFI
118
119#define CONFIG_SYS_MAX_FLASH_SECT 256
120#define CONFIG_SYS_MONITOR_BASE 0
121#define CONFIG_SYS_FLASH_BASE 0
122
123/*
124 * flash_toggle does not work for out supoort card.
125 * We need to use flash_status_poll.
126 */
127#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
128
129#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
130
Masahiro Yamada88216812014-12-06 00:03:26 +0900131#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900132
133/* serial console configuration */
134#define CONFIG_BAUDRATE 115200
135
136#define CONFIG_SYS_GENERIC_BOARD
137
138#if !defined(CONFIG_SPL_BUILD)
139#define CONFIG_USE_ARCH_MEMSET
140#define CONFIG_USE_ARCH_MEMCPY
141#endif
142
143#define CONFIG_SYS_LONGHELP /* undef to save memory */
144
145#define CONFIG_CMDLINE_EDITING /* add command line history */
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900146#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
147/* Print Buffer Size */
148#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
149#define CONFIG_SYS_MAXARGS 16 /* max number of command */
150/* Boot Argument Buffer Size */
151#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
152
153#define CONFIG_CONS_INDEX 1
154
155/*
156 * For NAND booting the environment is embedded in the U-Boot image. Please take
157 * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
158 */
159/* #define CONFIG_ENV_IS_IN_NAND */
160#define CONFIG_ENV_IS_NOWHERE
161#define CONFIG_ENV_SIZE 0x2000
162#define CONFIG_ENV_OFFSET 0x0
163/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
164
165/* Time clock 1MHz */
166#define CONFIG_SYS_TIMER_RATE 1000000
167
168/*
169 * By default, ARP timeout is 5 sec.
170 * The first ARP request does not seem to work.
171 * So we need to retry ARP request anyway.
172 * We want to shrink the interval until the second ARP request.
173 */
174#define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */
175
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900176#define CONFIG_SYS_MAX_NAND_DEVICE 1
177#define CONFIG_SYS_NAND_MAX_CHIPS 2
178#define CONFIG_SYS_NAND_ONFI_DETECTION
179
180#define CONFIG_NAND_DENALI_ECC_SIZE 1024
181
182#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
183#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
184
185#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
186
187#define CONFIG_SYS_NAND_USE_FLASH_BBT
188#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
189
Masahiro Yamada0b7e1df2014-11-07 18:48:34 +0900190/* USB */
Masahiro Yamada0b7e1df2014-11-07 18:48:34 +0900191#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Masahiro Yamadad50f3362015-02-27 02:27:01 +0900192#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
Masahiro Yamada0b7e1df2014-11-07 18:48:34 +0900193#define CONFIG_CMD_FAT
194#define CONFIG_FAT_WRITE
195#define CONFIG_DOS_PARTITION
196
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900197/* memtest works on */
198#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
199#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
200
201#define CONFIG_BOOTDELAY 3
202#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
203#define CONFIG_AUTOBOOT_KEYED 1
204#define CONFIG_AUTOBOOT_PROMPT \
205 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
206#define CONFIG_AUTOBOOT_DELAY_STR "d"
207#define CONFIG_AUTOBOOT_STOP_STR " "
208
209/*
210 * Network Configuration
211 */
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900212#define CONFIG_SERVERIP 192.168.11.1
213#define CONFIG_IPADDR 192.168.11.10
214#define CONFIG_GATEWAYIP 192.168.11.1
215#define CONFIG_NETMASK 255.255.255.0
216
217#define CONFIG_LOADADDR 0x84000000
218#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
219#define CONFIG_BOOTFILE "fit.itb"
220
221#define CONFIG_CMDLINE_EDITING /* add command line history */
222
223#define CONFIG_BOOTCOMMAND "run $bootmode"
224
225#define CONFIG_ROOTPATH "/nfs/root/path"
226#define CONFIG_NFSBOOTCOMMAND \
227 "setenv bootargs $bootargs root=/dev/nfs rw " \
228 "nfsroot=$serverip:$rootpath " \
229 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
230 "tftpboot; bootm;"
231
232#define CONFIG_BOOTARGS " user_debug=0x1f init=/sbin/init"
233
234#define CONFIG_EXTRA_ENV_SETTINGS \
235 "netdev=eth0\0" \
236 "image_offset=0x00080000\0" \
237 "image_size=0x00f00000\0" \
238 "verify=n\0" \
Masahiro Yamada5fc39942015-02-05 14:30:22 +0900239 "nandupdate=nand erase 0 0x100000 &&" \
240 "tftpboot u-boot-spl.bin &&" \
241 "nand write $loadaddr 0 0x10000 &&" \
242 "tftpboot u-boot-dtb.img &&" \
243 "nand write $loadaddr 0x10000 0xf0000\0" \
Masahiro Yamada860f2f82015-02-05 14:30:21 +0900244 "norboot=run add_default_bootargs &&" \
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900245 "bootm $image_offset\0" \
Masahiro Yamada860f2f82015-02-05 14:30:21 +0900246 "nandboot=run add_default_bootargs &&" \
247 "nand read $loadaddr $image_offset $image_size &&" \
248 "bootm\0" \
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900249 "add_default_bootargs=setenv bootargs $bootargs" \
250 " console=ttyS0,$baudrate\0" \
251
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900252/* Open Firmware flat tree */
253#define CONFIG_OF_LIBFDT
254
255#define CONFIG_HAVE_ARM_SECURE
256
257/* Memory Size & Mapping */
258#define CONFIG_SYS_SDRAM_BASE CONFIG_SDRAM0_BASE
259
260#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
261/* Thre is no memory hole */
262#define CONFIG_NR_DRAM_BANKS 1
263#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
264#else
265#define CONFIG_NR_DRAM_BANKS 2
266#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE)
267#endif
268
269#define CONFIG_SYS_TEXT_BASE 0x84000000
270
Masahiro Yamada1e72b1c2014-12-06 00:03:22 +0900271#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
272#define CONFIG_SPL_TEXT_BASE 0x00040000
273#endif
274#if defined(CONFIG_MACH_PH1_PRO4)
275#define CONFIG_SPL_TEXT_BASE 0x00100000
276#endif
277
Masahiro Yamada5b01ec42015-03-23 00:07:26 +0900278#define CONFIG_SPL_STACK (0x0ff08000)
Masahiro Yamada424e7822015-03-23 00:07:28 +0900279#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900280
Masahiro Yamada37797532015-03-23 00:07:24 +0900281#define CONFIG_PANIC_HANG
282
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900283#define CONFIG_SPL_FRAMEWORK
Masahiro Yamada6b23db82015-03-23 00:07:25 +0900284#define CONFIG_SPL_SERIAL_SUPPORT
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900285#define CONFIG_SPL_NAND_SUPPORT
286
287#define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */
288#define CONFIG_SPL_LIBGENERIC_SUPPORT
289
290#define CONFIG_SPL_BOARD_INIT
291
292#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
293
Masahiro Yamadab4f865d2015-03-23 00:07:27 +0900294#define CONFIG_SPL_MAX_FOOTPRINT 0x10000
295
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900296#endif /* __CONFIG_UNIPHIER_COMMON_H__ */