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wdenk7ac16102004-08-01 22:48:16 +00001/*
2 * Copyright (C) 2003 ETC s.r.o.
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
wdenk7ac16102004-08-01 22:48:16 +00005 * Written by Peter Figuli <peposh@etc.sk>, 2003.
6 *
7 * 2003/13/06 Initial MP10 Support copied from wepep250
8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Masahiro Yamada7a5b2922014-11-06 14:59:35 +090013#define CONFIG_IMX 1 /* This is a Motorola MC9328MXL Chip */
wdenk7ac16102004-08-01 22:48:16 +000014#define CONFIG_SCB9328 1 /* on a scb9328tronix board */
wdenk7ac16102004-08-01 22:48:16 +000015
Jean-Christophe PLAGNIOL-VILLARDa3fe0172009-03-30 18:58:38 +020016#define CONFIG_IMX_SERIAL
wdenk7ac16102004-08-01 22:48:16 +000017#define CONFIG_IMX_SERIAL1
18/*
19 * Select serial console configuration
20 */
21
wdenk7ac16102004-08-01 22:48:16 +000022/*
Jon Loeliger5c4ddae2007-07-10 10:12:10 -050023 * BOOTP options
24 */
25#define CONFIG_BOOTP_BOOTFILESIZE
26#define CONFIG_BOOTP_BOOTPATH
27#define CONFIG_BOOTP_GATEWAY
28#define CONFIG_BOOTP_HOSTNAME
29
Jon Loeliger5c4ddae2007-07-10 10:12:10 -050030/*
Jon Loeliger49851be2007-07-04 22:33:30 -050031 * Command line configuration.
wdenk7ac16102004-08-01 22:48:16 +000032 */
Jon Loeliger49851be2007-07-04 22:33:30 -050033#include <config_cmd_default.h>
34
35#define CONFIG_CMD_NET
36#define CONFIG_CMD_PING
37#define CONFIG_CMD_DHCP
38
Jon Loeliger49851be2007-07-04 22:33:30 -050039#undef CONFIG_CMD_CONSOLE
Wolfgang Denk85c25df2009-04-01 23:34:12 +020040#undef CONFIG_CMD_LOADS
41#undef CONFIG_CMD_SOURCE
wdenk7ac16102004-08-01 22:48:16 +000042
wdenk7ac16102004-08-01 22:48:16 +000043/*
44 * Boot options. Setting delay to -1 stops autostart count down.
45 * NOTE: Sending parameters to kernel depends on kernel version and
46 * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
47 * parameters at all! Do not get confused by them so.
48 */
49#define CONFIG_BOOTDELAY -1
50#define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328"
51#define CONFIG_BOOTCOMMAND "bootm 10040000"
52#define CONFIG_SHOW_BOOT_PROGRESS
wdenk7ac16102004-08-01 22:48:16 +000053#define CONFIG_NETMASK 255.255.255.0
54#define CONFIG_IPADDR 10.10.10.9
55#define CONFIG_SERVERIP 10.10.10.10
56
57/*
58 * General options for u-boot. Modify to save memory foot print
59 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020060#define CONFIG_SYS_LONGHELP /* undef saves memory */
61#define CONFIG_SYS_PROMPT "scb9328> " /* prompt string */
62#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */
63#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */
64#define CONFIG_SYS_MAXARGS 16 /* max command args */
65#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */
wdenk7ac16102004-08-01 22:48:16 +000066
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020067#define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */
68#define CONFIG_SYS_MEMTEST_END 0x08F00000
wdenk7ac16102004-08-01 22:48:16 +000069
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020070#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */
wdenk7ac16102004-08-01 22:48:16 +000071
wdenk7ac16102004-08-01 22:48:16 +000072#define CONFIG_BAUDRATE 115200
73/*
74 * Definitions related to passing arguments to kernel.
75 */
76#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
77#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
78#define CONFIG_INITRD_TAG 1 /* send initrd params */
wdenk7ac16102004-08-01 22:48:16 +000079
wdenk7ac16102004-08-01 22:48:16 +000080/*
81 * Malloc pool need to host env + 128 Kb reserve for other allocations.
82 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020083#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) )
wdenk7ac16102004-08-01 22:48:16 +000084
wdenk7ac16102004-08-01 22:48:16 +000085/* SDRAM Setup Values
860x910a8300 Precharge Command CAS 3
870x910a8200 Precharge Command CAS 2
88
890xa10a8300 AutoRefresh Command CAS 3
900xa10a8200 Set AutoRefresh Command CAS 2 */
91
92#define PRECHARGE_CMD 0x910a8200
93#define AUTOREFRESH_CMD 0xa10a8200
wdenk7ac16102004-08-01 22:48:16 +000094
95/*
96 * SDRAM Memory Map
97 */
98/* SH FIXME */
99#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
100#define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */
101#define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */
102
Torsten Koschorrek253c3ef2011-07-14 23:16:51 +0000103#define CONFIG_SYS_TEXT_BASE 0x10000000
104
105#define CONFIG_SYS_SDRAM_BASE SCB9328_SDRAM_1
106#define CONFIG_SYS_INIT_SP_ADDR (SCB9328_SDRAM_1 + 0xf00000)
107
wdenk7ac16102004-08-01 22:48:16 +0000108/*
wdenk7ac16102004-08-01 22:48:16 +0000109 * Configuration for FLASH memory for the Synertronixx board
110 */
111
112/* #define SCB9328_FLASH_32M */
113
114/* 32MB */
115#ifdef SCB9328_FLASH_32M
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
117#define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */
wdenk7ac16102004-08-01 22:48:16 +0000118#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
119#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
120#define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */
121#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
122#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
123#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
124#else
125
126/* 16MB */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
128#define CONFIG_SYS_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */
wdenk7ac16102004-08-01 22:48:16 +0000129#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
130#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
131#define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */
132#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
133#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
134#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
135#endif /* SCB9328_FLASH_32M */
136
137/* This should be defined if CFI FLASH device is present. Actually benefit
138 is not so clear to me. In other words we can provide more informations
139 to user, but this expects more complex flash handling we do not provide
140 now.*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200141#undef CONFIG_SYS_FLASH_CFI
wdenk7ac16102004-08-01 22:48:16 +0000142
Marek Vasut7982fe52013-11-04 20:50:21 +0100143#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* timeout for Erase operation */
144#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 /* timeout for Write operation */
wdenk7ac16102004-08-01 22:48:16 +0000145
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200146#define CONFIG_SYS_FLASH_BASE SCB9328_FLASH_BASE
wdenk7ac16102004-08-01 22:48:16 +0000147
148/*
149 * This is setting for JFFS2 support in u-boot.
150 * Right now there is no gain for user, but later on booting kernel might be
151 * possible. Consider using XIP kernel running from flash to save RAM
152 * footprint.
Jon Loeliger5c4ddae2007-07-10 10:12:10 -0500153 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
wdenk7ac16102004-08-01 22:48:16 +0000154 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200155#define CONFIG_SYS_JFFS2_FIRST_BANK 0
156#define CONFIG_SYS_JFFS2_FIRST_SECTOR 5
157#define CONFIG_SYS_JFFS2_NUM_BANKS 1
wdenk7ac16102004-08-01 22:48:16 +0000158
159/*
160 * Environment setup. Definitions of monitor location and size with
161 * definition of environment setup ends up in 2 possibilities.
162 * 1. Embeded environment - in u-boot code is space for environment
163 * 2. Environment is read from predefined sector of flash
164 * Right now we support 2. possiblity, but expecting no env placed
165 * on mentioned address right now. This also needs to provide whole
166 * sector for it - for us 256Kb is really waste of memory. U-boot uses
167 * default env. and until kernel parameters could be sent to kernel
168 * env. has no sense to us.
169 */
170
171/* Setup for PA23 which is Reset Default PA23 but has to become
172 CS5 */
173
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200174#define CONFIG_SYS_GPR_A_VAL 0x00800000
175#define CONFIG_SYS_GIUS_A_VAL 0x0043fffe
wdenk7ac16102004-08-01 22:48:16 +0000176
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200177#define CONFIG_SYS_MONITOR_BASE 0x10000000
178#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200179#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200180#define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */
181#define CONFIG_ENV_SIZE 0x20000
wdenk7ac16102004-08-01 22:48:16 +0000182
183#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */
184
185/*
186 * CSxU_VAL:
187 * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32
188 * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC |
189 *
190 * CSxL_VAL:
191 * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0
192 * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN|
193 */
194
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200195#define CONFIG_SYS_CS0U_VAL 0x000F2000
196#define CONFIG_SYS_CS0L_VAL 0x11110d01
197#define CONFIG_SYS_CS1U_VAL 0x000F0a00
198#define CONFIG_SYS_CS1L_VAL 0x11110601
199#define CONFIG_SYS_CS2U_VAL 0x0
200#define CONFIG_SYS_CS2L_VAL 0x0
wdenk7ac16102004-08-01 22:48:16 +0000201
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202#define CONFIG_SYS_CS3U_VAL 0x000FFFFF
203#define CONFIG_SYS_CS3L_VAL 0x00000303
wdenk7ac16102004-08-01 22:48:16 +0000204
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200205#define CONFIG_SYS_CS4U_VAL 0x000F0a00
206#define CONFIG_SYS_CS4L_VAL 0x11110301
wdenk7ac16102004-08-01 22:48:16 +0000207
208/* CNC == 3 too long
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200209 #define CONFIG_SYS_CS5U_VAL 0x0000C210 */
wdenk7ac16102004-08-01 22:48:16 +0000210
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200211/* #define CONFIG_SYS_CS5U_VAL 0x00008400
wdenk7ac16102004-08-01 22:48:16 +0000212 mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
213 kaum langsamer ist */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200214/* #define CONFIG_SYS_CS5U_VAL 0x00009400
215 #define CONFIG_SYS_CS5L_VAL 0x11010D03 */
wdenk7ac16102004-08-01 22:48:16 +0000216
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200217#define CONFIG_SYS_CS5U_VAL 0x00008400
218#define CONFIG_SYS_CS5L_VAL 0x00000D03
wdenk7ac16102004-08-01 22:48:16 +0000219
220#define CONFIG_DRIVER_DM9000 1
wdenk7ac16102004-08-01 22:48:16 +0000221#define CONFIG_DM9000_BASE 0x16000000
222#define DM9000_IO CONFIG_DM9000_BASE
223#define DM9000_DATA (CONFIG_DM9000_BASE+4)
wdenk7ac16102004-08-01 22:48:16 +0000224
225/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
226 f_ref=16,777MHz
227
228 0x002a141f: 191,9944MHz
229 0x040b2007: 144MHz
230 0x042a141f: 96MHz
231 0x0811140d: 64MHz
232 0x040e200e: 150MHz
233 0x00321431: 200MHz
234
235 0x08001800: 64MHz mit 16er Quarz
236 0x04001800: 96MHz mit 16er Quarz
237 0x04002400: 144MHz mit 16er Quarz
238
239 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
240 |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */
241
242#define CPU200
243
244#ifdef CPU200
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200245#define CONFIG_SYS_MPCTL0_VAL 0x00321431
wdenk7ac16102004-08-01 22:48:16 +0000246#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200247#define CONFIG_SYS_MPCTL0_VAL 0x040e200e
wdenk7ac16102004-08-01 22:48:16 +0000248#endif
249
250/* #define BUS64 */
251#define BUS72
252
253#ifdef BUS72
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200254#define CONFIG_SYS_SPCTL0_VAL 0x04002400
wdenk7ac16102004-08-01 22:48:16 +0000255#endif
256
257#ifdef BUS96
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200258#define CONFIG_SYS_SPCTL0_VAL 0x04001800
wdenk7ac16102004-08-01 22:48:16 +0000259#endif
260
261#ifdef BUS64
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200262#define CONFIG_SYS_SPCTL0_VAL 0x08001800
wdenk7ac16102004-08-01 22:48:16 +0000263#endif
264
265/* Das ist der BCLK Divider, der aus der System PLL
266 BCLK und HCLK erzeugt:
267 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
268 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
269 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
270 0x2f001003 : 192MHz/5=38,4MHz
271 0x2f000003 : 64MHz/1
272 Bit 22: SPLL Restart
273 Bit 21: MPLL Restart */
274
275#ifdef BUS64
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200276#define CONFIG_SYS_CSCR_VAL 0x2f030003
wdenk7ac16102004-08-01 22:48:16 +0000277#endif
278
279#ifdef BUS72
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200280#define CONFIG_SYS_CSCR_VAL 0x2f030403
wdenk7ac16102004-08-01 22:48:16 +0000281#endif
282
283/*
284 * Well this has to be defined, but on the other hand it is used differently
285 * one may expect. For instance loadb command do not cares :-)
286 * So advice is - do not relay on this...
287 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200288#define CONFIG_SYS_LOAD_ADDR 0x08400000
wdenk7ac16102004-08-01 22:48:16 +0000289
290#define MHZ16QUARZINUSE
291
292#ifdef MHZ16QUARZINUSE
293#define CONFIG_SYSPLL_CLK_FREQ 16000000
294#else
295#define CONFIG_SYSPLL_CLK_FREQ 16780000
296#endif
297
298#define CONFIG_SYS_CLK_FREQ 16780000
299
300/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200301#define CONFIG_SYS_FMCR_VAL 0x00000001
wdenk7ac16102004-08-01 22:48:16 +0000302
303/* Bit[0:3] contain PERCLK1DIV for UART 1
304 0x000b00b ->b<- -> 192MHz/12=16MHz
305 0x000b00b ->8<- -> 144MHz/09=16MHz
306 0x000b00b ->3<- -> 64MHz/4=16MHz */
307
308#ifdef BUS96
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200309#define CONFIG_SYS_PCDR_VAL 0x000b00b5
wdenk7ac16102004-08-01 22:48:16 +0000310#endif
311
312#ifdef BUS64
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200313#define CONFIG_SYS_PCDR_VAL 0x000b00b3
wdenk7ac16102004-08-01 22:48:16 +0000314#endif
315
316#ifdef BUS72
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200317#define CONFIG_SYS_PCDR_VAL 0x000b00b8
wdenk7ac16102004-08-01 22:48:16 +0000318#endif
319
320#endif /* __CONFIG_H */