Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2014 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #ifndef __CONFIG_H |
| 8 | #define __CONFIG_H |
| 9 | |
| 10 | #include <config_cmd_default.h> |
| 11 | |
| 12 | #define CONFIG_LS102XA |
| 13 | |
| 14 | #define CONFIG_SYS_GENERIC_BOARD |
| 15 | |
| 16 | #define CONFIG_DISPLAY_CPUINFO |
| 17 | #define CONFIG_DISPLAY_BOARDINFO |
| 18 | |
| 19 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 20 | #define CONFIG_BOARD_EARLY_INIT_F |
| 21 | |
tang yuantian | 57296e7 | 2014-12-17 12:58:05 +0800 | [diff] [blame] | 22 | #define CONFIG_DEEP_SLEEP |
| 23 | #if defined(CONFIG_DEEP_SLEEP) |
| 24 | #define CONFIG_SILENT_CONSOLE |
| 25 | #endif |
| 26 | |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 27 | /* |
| 28 | * Size of malloc() pool |
| 29 | */ |
| 30 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) |
| 31 | |
| 32 | #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR |
| 33 | #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE |
| 34 | |
| 35 | /* |
| 36 | * Generic Timer Definitions |
| 37 | */ |
| 38 | #define GENERIC_TIMER_CLK 12500000 |
| 39 | |
| 40 | #ifndef __ASSEMBLY__ |
| 41 | unsigned long get_board_sys_clk(void); |
| 42 | unsigned long get_board_ddr_clk(void); |
| 43 | #endif |
| 44 | |
Alison Wang | 2145a37 | 2014-12-09 17:38:02 +0800 | [diff] [blame] | 45 | #ifdef CONFIG_QSPI_BOOT |
| 46 | #define CONFIG_SYS_CLK_FREQ 100000000 |
| 47 | #define CONFIG_DDR_CLK_FREQ 100000000 |
| 48 | #define CONFIG_QIXIS_I2C_ACCESS |
| 49 | #else |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 50 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() |
| 51 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() |
Alison Wang | 2145a37 | 2014-12-09 17:38:02 +0800 | [diff] [blame] | 52 | #endif |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 53 | |
Alison Wang | 9da5178 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 54 | #ifdef CONFIG_RAMBOOT_PBL |
| 55 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg |
| 56 | #endif |
| 57 | |
| 58 | #ifdef CONFIG_SD_BOOT |
| 59 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg |
| 60 | #define CONFIG_SPL_FRAMEWORK |
| 61 | #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" |
| 62 | #define CONFIG_SPL_LIBCOMMON_SUPPORT |
| 63 | #define CONFIG_SPL_LIBGENERIC_SUPPORT |
| 64 | #define CONFIG_SPL_ENV_SUPPORT |
| 65 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT |
| 66 | #define CONFIG_SPL_I2C_SUPPORT |
| 67 | #define CONFIG_SPL_WATCHDOG_SUPPORT |
| 68 | #define CONFIG_SPL_SERIAL_SUPPORT |
| 69 | #define CONFIG_SPL_DRIVERS_MISC_SUPPORT |
| 70 | #define CONFIG_SPL_MMC_SUPPORT |
| 71 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 |
| 72 | #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 |
| 73 | |
| 74 | #define CONFIG_SPL_TEXT_BASE 0x10000000 |
| 75 | #define CONFIG_SPL_MAX_SIZE 0x1a000 |
| 76 | #define CONFIG_SPL_STACK 0x1001d000 |
| 77 | #define CONFIG_SPL_PAD_TO 0x1c000 |
| 78 | #define CONFIG_SYS_TEXT_BASE 0x82000000 |
| 79 | |
tang yuantian | 57296e7 | 2014-12-17 12:58:05 +0800 | [diff] [blame] | 80 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ |
| 81 | CONFIG_SYS_MONITOR_LEN) |
Alison Wang | 9da5178 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 82 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 |
| 83 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 |
| 84 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
| 85 | #define CONFIG_SYS_MONITOR_LEN 0x80000 |
| 86 | #endif |
| 87 | |
Alison Wang | 2145a37 | 2014-12-09 17:38:02 +0800 | [diff] [blame] | 88 | #ifdef CONFIG_QSPI_BOOT |
| 89 | #define CONFIG_SYS_TEXT_BASE 0x40010000 |
| 90 | #define CONFIG_SYS_NO_FLASH |
| 91 | #endif |
| 92 | |
Alison Wang | ab98bb5 | 2014-12-09 17:38:14 +0800 | [diff] [blame] | 93 | #ifdef CONFIG_NAND_BOOT |
| 94 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg |
| 95 | #define CONFIG_SPL_FRAMEWORK |
| 96 | #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" |
| 97 | #define CONFIG_SPL_LIBCOMMON_SUPPORT |
| 98 | #define CONFIG_SPL_LIBGENERIC_SUPPORT |
| 99 | #define CONFIG_SPL_ENV_SUPPORT |
| 100 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT |
| 101 | #define CONFIG_SPL_I2C_SUPPORT |
| 102 | #define CONFIG_SPL_WATCHDOG_SUPPORT |
| 103 | #define CONFIG_SPL_SERIAL_SUPPORT |
| 104 | #define CONFIG_SPL_NAND_SUPPORT |
| 105 | #define CONFIG_SPL_DRIVERS_MISC_SUPPORT |
| 106 | |
| 107 | #define CONFIG_SPL_TEXT_BASE 0x10000000 |
| 108 | #define CONFIG_SPL_MAX_SIZE 0x1a000 |
| 109 | #define CONFIG_SPL_STACK 0x1001d000 |
| 110 | #define CONFIG_SPL_PAD_TO 0x1c000 |
| 111 | #define CONFIG_SYS_TEXT_BASE 0x82000000 |
| 112 | |
| 113 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) |
| 114 | #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO |
| 115 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 |
| 116 | #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE |
| 117 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE |
| 118 | |
| 119 | #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 |
| 120 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 |
| 121 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 |
| 122 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
| 123 | #define CONFIG_SYS_MONITOR_LEN 0x80000 |
| 124 | #endif |
| 125 | |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 126 | #ifndef CONFIG_SYS_TEXT_BASE |
Alison Wang | 4d786e8 | 2015-04-21 16:04:38 +0800 | [diff] [blame] | 127 | #define CONFIG_SYS_TEXT_BASE 0x60100000 |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 128 | #endif |
| 129 | |
| 130 | #define CONFIG_NR_DRAM_BANKS 1 |
| 131 | |
| 132 | #define CONFIG_DDR_SPD |
| 133 | #define SPD_EEPROM_ADDRESS 0x51 |
| 134 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 135 | |
| 136 | #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ |
York Sun | ba3c080 | 2014-09-11 13:32:07 -0700 | [diff] [blame] | 137 | #ifndef CONFIG_SYS_FSL_DDR4 |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 138 | #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ |
York Sun | ba3c080 | 2014-09-11 13:32:07 -0700 | [diff] [blame] | 139 | #define CONFIG_SYS_DDR_RAW_TIMING |
| 140 | #endif |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 141 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 142 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 |
| 143 | |
| 144 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL |
| 145 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| 146 | |
| 147 | #define CONFIG_DDR_ECC |
| 148 | #ifdef CONFIG_DDR_ECC |
| 149 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
| 150 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
| 151 | #endif |
| 152 | |
| 153 | #define CONFIG_SYS_HAS_SERDES |
| 154 | |
Ruchika Gupta | 901ae76 | 2014-10-15 11:39:06 +0530 | [diff] [blame] | 155 | #define CONFIG_FSL_CAAM /* Enable CAAM */ |
Zhao Qiang | 9fc2f30 | 2014-09-26 16:25:32 +0800 | [diff] [blame] | 156 | |
Alison Wang | a5494fb | 2014-12-09 17:37:49 +0800 | [diff] [blame] | 157 | #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ |
| 158 | !defined(CONFIG_QSPI_BOOT) |
Zhao Qiang | 9fc2f30 | 2014-09-26 16:25:32 +0800 | [diff] [blame] | 159 | #define CONFIG_U_QE |
| 160 | #endif |
| 161 | |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 162 | /* |
| 163 | * IFC Definitions |
| 164 | */ |
Alison Wang | 2145a37 | 2014-12-09 17:38:02 +0800 | [diff] [blame] | 165 | #ifndef CONFIG_QSPI_BOOT |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 166 | #define CONFIG_FSL_IFC |
| 167 | #define CONFIG_SYS_FLASH_BASE 0x60000000 |
| 168 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| 169 | |
| 170 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) |
| 171 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ |
| 172 | CSPR_PORT_SIZE_16 | \ |
| 173 | CSPR_MSEL_NOR | \ |
| 174 | CSPR_V) |
| 175 | #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) |
| 176 | #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ |
| 177 | + 0x8000000) | \ |
| 178 | CSPR_PORT_SIZE_16 | \ |
| 179 | CSPR_MSEL_NOR | \ |
| 180 | CSPR_V) |
| 181 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) |
| 182 | |
| 183 | #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ |
| 184 | CSOR_NOR_TRHZ_80) |
| 185 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ |
| 186 | FTIM0_NOR_TEADC(0x5) | \ |
| 187 | FTIM0_NOR_TEAHC(0x5)) |
| 188 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ |
| 189 | FTIM1_NOR_TRAD_NOR(0x1a) | \ |
| 190 | FTIM1_NOR_TSEQRAD_NOR(0x13)) |
| 191 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ |
| 192 | FTIM2_NOR_TCH(0x4) | \ |
| 193 | FTIM2_NOR_TWPH(0xe) | \ |
| 194 | FTIM2_NOR_TWP(0x1c)) |
| 195 | #define CONFIG_SYS_NOR_FTIM3 0 |
| 196 | |
| 197 | #define CONFIG_FLASH_CFI_DRIVER |
| 198 | #define CONFIG_SYS_FLASH_CFI |
| 199 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
| 200 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 201 | #define CONFIG_FLASH_SHOW_PROGRESS 45 |
| 202 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS |
Yuan Yao | da17d1a | 2014-10-17 15:26:34 +0800 | [diff] [blame] | 203 | #define CONFIG_SYS_WRITE_SWAPPED_DATA |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 204 | |
| 205 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 206 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
| 207 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 208 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 209 | |
| 210 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 211 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ |
| 212 | CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} |
| 213 | |
| 214 | /* |
| 215 | * NAND Flash Definitions |
| 216 | */ |
| 217 | #define CONFIG_NAND_FSL_IFC |
| 218 | |
| 219 | #define CONFIG_SYS_NAND_BASE 0x7e800000 |
| 220 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| 221 | |
| 222 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) |
| 223 | |
| 224 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 225 | | CSPR_PORT_SIZE_8 \ |
| 226 | | CSPR_MSEL_NAND \ |
| 227 | | CSPR_V) |
| 228 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) |
| 229 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
| 230 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ |
| 231 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ |
| 232 | | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ |
| 233 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ |
| 234 | | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ |
| 235 | | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ |
| 236 | |
| 237 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
| 238 | |
| 239 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ |
| 240 | FTIM0_NAND_TWP(0x18) | \ |
| 241 | FTIM0_NAND_TWCHT(0x7) | \ |
| 242 | FTIM0_NAND_TWH(0xa)) |
| 243 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
| 244 | FTIM1_NAND_TWBE(0x39) | \ |
| 245 | FTIM1_NAND_TRR(0xe) | \ |
| 246 | FTIM1_NAND_TRP(0x18)) |
| 247 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ |
| 248 | FTIM2_NAND_TREH(0xa) | \ |
| 249 | FTIM2_NAND_TWHRE(0x1e)) |
| 250 | #define CONFIG_SYS_NAND_FTIM3 0x0 |
| 251 | |
| 252 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
| 253 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 254 | #define CONFIG_CMD_NAND |
| 255 | |
| 256 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
Alison Wang | 2145a37 | 2014-12-09 17:38:02 +0800 | [diff] [blame] | 257 | #endif |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 258 | |
| 259 | /* |
| 260 | * QIXIS Definitions |
| 261 | */ |
| 262 | #define CONFIG_FSL_QIXIS |
| 263 | |
| 264 | #ifdef CONFIG_FSL_QIXIS |
| 265 | #define QIXIS_BASE 0x7fb00000 |
| 266 | #define QIXIS_BASE_PHYS QIXIS_BASE |
| 267 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 |
| 268 | #define QIXIS_LBMAP_SWITCH 6 |
| 269 | #define QIXIS_LBMAP_MASK 0x0f |
| 270 | #define QIXIS_LBMAP_SHIFT 0 |
| 271 | #define QIXIS_LBMAP_DFLTBANK 0x00 |
| 272 | #define QIXIS_LBMAP_ALTBANK 0x04 |
| 273 | #define QIXIS_RST_CTL_RESET 0x44 |
| 274 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 |
| 275 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 |
| 276 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 |
| 277 | |
| 278 | #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) |
| 279 | #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ |
| 280 | CSPR_PORT_SIZE_8 | \ |
| 281 | CSPR_MSEL_GPCM | \ |
| 282 | CSPR_V) |
| 283 | #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) |
| 284 | #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ |
| 285 | CSOR_NOR_NOR_MODE_AVD_NOR | \ |
| 286 | CSOR_NOR_TRHZ_80) |
| 287 | |
| 288 | /* |
| 289 | * QIXIS Timing parameters for IFC GPCM |
| 290 | */ |
| 291 | #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ |
| 292 | FTIM0_GPCM_TEADC(0xe) | \ |
| 293 | FTIM0_GPCM_TEAHC(0xe)) |
| 294 | #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ |
| 295 | FTIM1_GPCM_TRAD(0x1f)) |
| 296 | #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ |
| 297 | FTIM2_GPCM_TCH(0xe) | \ |
| 298 | FTIM2_GPCM_TWP(0xf0)) |
| 299 | #define CONFIG_SYS_FPGA_FTIM3 0x0 |
| 300 | #endif |
| 301 | |
Alison Wang | ab98bb5 | 2014-12-09 17:38:14 +0800 | [diff] [blame] | 302 | #if defined(CONFIG_NAND_BOOT) |
| 303 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 304 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
| 305 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK |
| 306 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR |
| 307 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 308 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 309 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 310 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 |
| 311 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT |
| 312 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR |
| 313 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK |
| 314 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR |
| 315 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 316 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 317 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 318 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 319 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT |
| 320 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR |
| 321 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK |
| 322 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR |
| 323 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 324 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 325 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 326 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 327 | #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT |
| 328 | #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR |
| 329 | #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK |
| 330 | #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR |
| 331 | #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 |
| 332 | #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 |
| 333 | #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 |
| 334 | #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 |
| 335 | #else |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 336 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
| 337 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR |
| 338 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
| 339 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
| 340 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 341 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 342 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 343 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 344 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT |
| 345 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR |
| 346 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK |
| 347 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR |
| 348 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 349 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 350 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 351 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 352 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 353 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR |
| 354 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK |
| 355 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR |
| 356 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 357 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 358 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 359 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 |
| 360 | #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT |
| 361 | #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR |
| 362 | #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK |
| 363 | #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR |
| 364 | #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 |
| 365 | #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 |
| 366 | #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 |
| 367 | #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 |
Alison Wang | ab98bb5 | 2014-12-09 17:38:14 +0800 | [diff] [blame] | 368 | #endif |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 369 | |
| 370 | /* |
| 371 | * Serial Port |
| 372 | */ |
Alison Wang | e2f33ae | 2015-01-04 15:30:58 +0800 | [diff] [blame] | 373 | #ifdef CONFIG_LPUART |
| 374 | #define CONFIG_FSL_LPUART |
| 375 | #define CONFIG_LPUART_32B_REG |
| 376 | #else |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 377 | #define CONFIG_CONS_INDEX 1 |
| 378 | #define CONFIG_SYS_NS16550 |
| 379 | #define CONFIG_SYS_NS16550_SERIAL |
| 380 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 381 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() |
Alison Wang | e2f33ae | 2015-01-04 15:30:58 +0800 | [diff] [blame] | 382 | #endif |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 383 | |
| 384 | #define CONFIG_BAUDRATE 115200 |
| 385 | |
| 386 | /* |
| 387 | * I2C |
| 388 | */ |
| 389 | #define CONFIG_CMD_I2C |
| 390 | #define CONFIG_SYS_I2C |
| 391 | #define CONFIG_SYS_I2C_MXC |
York Sun | f1a5216 | 2015-03-20 10:20:40 -0700 | [diff] [blame] | 392 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 393 | |
| 394 | /* |
| 395 | * I2C bus multiplexer |
| 396 | */ |
| 397 | #define I2C_MUX_PCA_ADDR_PRI 0x77 |
| 398 | #define I2C_MUX_CH_DEFAULT 0x8 |
Xiubo Li | 27e2fe6 | 2014-12-16 14:50:33 +0800 | [diff] [blame] | 399 | #define I2C_MUX_CH_CH7301 0xC |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 400 | |
| 401 | /* |
| 402 | * MMC |
| 403 | */ |
| 404 | #define CONFIG_MMC |
| 405 | #define CONFIG_CMD_MMC |
| 406 | #define CONFIG_FSL_ESDHC |
| 407 | #define CONFIG_GENERIC_MMC |
| 408 | |
Alison Wang | befe688 | 2014-12-09 17:37:34 +0800 | [diff] [blame] | 409 | #define CONFIG_CMD_FAT |
| 410 | #define CONFIG_DOS_PARTITION |
| 411 | |
Alison Wang | 2145a37 | 2014-12-09 17:38:02 +0800 | [diff] [blame] | 412 | /* QSPI */ |
| 413 | #ifdef CONFIG_QSPI_BOOT |
| 414 | #define CONFIG_FSL_QSPI |
| 415 | #define QSPI0_AMBA_BASE 0x40000000 |
| 416 | #define FSL_QSPI_FLASH_SIZE (1 << 24) |
| 417 | #define FSL_QSPI_FLASH_NUM 2 |
| 418 | |
| 419 | #define CONFIG_CMD_SF |
| 420 | #define CONFIG_SPI_FLASH |
| 421 | #define CONFIG_SPI_FLASH_SPANSION |
| 422 | #endif |
| 423 | |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 424 | /* |
Nikhil Badola | 4da7bae5 | 2014-10-17 11:37:25 +0530 | [diff] [blame] | 425 | * USB |
| 426 | */ |
| 427 | #define CONFIG_HAS_FSL_DR_USB |
| 428 | |
| 429 | #ifdef CONFIG_HAS_FSL_DR_USB |
| 430 | #define CONFIG_USB_EHCI |
| 431 | |
| 432 | #ifdef CONFIG_USB_EHCI |
| 433 | #define CONFIG_CMD_USB |
| 434 | #define CONFIG_USB_STORAGE |
| 435 | #define CONFIG_USB_EHCI_FSL |
| 436 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 437 | #define CONFIG_CMD_EXT2 |
| 438 | #endif |
| 439 | #endif |
| 440 | |
| 441 | /* |
Xiubo Li | 27e2fe6 | 2014-12-16 14:50:33 +0800 | [diff] [blame] | 442 | * Video |
| 443 | */ |
| 444 | #define CONFIG_FSL_DCU_FB |
| 445 | |
| 446 | #ifdef CONFIG_FSL_DCU_FB |
| 447 | #define CONFIG_VIDEO |
| 448 | #define CONFIG_CMD_BMP |
| 449 | #define CONFIG_CFB_CONSOLE |
| 450 | #define CONFIG_VGA_AS_SINGLE_DEVICE |
| 451 | #define CONFIG_VIDEO_LOGO |
| 452 | #define CONFIG_VIDEO_BMP_LOGO |
| 453 | |
| 454 | #define CONFIG_FSL_DIU_CH7301 |
| 455 | #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 |
| 456 | #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 |
| 457 | #define CONFIG_SYS_I2C_DVI_ADDR 0x75 |
| 458 | #endif |
| 459 | |
| 460 | /* |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 461 | * eTSEC |
| 462 | */ |
| 463 | #define CONFIG_TSEC_ENET |
| 464 | |
| 465 | #ifdef CONFIG_TSEC_ENET |
| 466 | #define CONFIG_MII |
| 467 | #define CONFIG_MII_DEFAULT_TSEC 3 |
| 468 | #define CONFIG_TSEC1 1 |
| 469 | #define CONFIG_TSEC1_NAME "eTSEC1" |
| 470 | #define CONFIG_TSEC2 1 |
| 471 | #define CONFIG_TSEC2_NAME "eTSEC2" |
| 472 | #define CONFIG_TSEC3 1 |
| 473 | #define CONFIG_TSEC3_NAME "eTSEC3" |
| 474 | |
| 475 | #define TSEC1_PHY_ADDR 1 |
| 476 | #define TSEC2_PHY_ADDR 2 |
| 477 | #define TSEC3_PHY_ADDR 3 |
| 478 | |
| 479 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 480 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 481 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 482 | |
| 483 | #define TSEC1_PHYIDX 0 |
| 484 | #define TSEC2_PHYIDX 0 |
| 485 | #define TSEC3_PHYIDX 0 |
| 486 | |
| 487 | #define CONFIG_ETHPRIME "eTSEC1" |
| 488 | |
| 489 | #define CONFIG_PHY_GIGE |
| 490 | #define CONFIG_PHYLIB |
| 491 | #define CONFIG_PHY_REALTEK |
| 492 | |
| 493 | #define CONFIG_HAS_ETH0 |
| 494 | #define CONFIG_HAS_ETH1 |
| 495 | #define CONFIG_HAS_ETH2 |
| 496 | |
| 497 | #define CONFIG_FSL_SGMII_RISER 1 |
| 498 | #define SGMII_RISER_PHY_OFFSET 0x1b |
| 499 | |
| 500 | #ifdef CONFIG_FSL_SGMII_RISER |
| 501 | #define CONFIG_SYS_TBIPA_VALUE 8 |
| 502 | #endif |
| 503 | |
| 504 | #endif |
Minghuan Lian | a4d6b61 | 2014-10-31 13:43:44 +0800 | [diff] [blame] | 505 | |
| 506 | /* PCIe */ |
| 507 | #define CONFIG_PCI /* Enable PCI/PCIE */ |
| 508 | #define CONFIG_PCIE1 /* PCIE controler 1 */ |
| 509 | #define CONFIG_PCIE2 /* PCIE controler 2 */ |
| 510 | #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ |
| 511 | #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" |
| 512 | |
Minghuan Lian | 0c1593a | 2015-01-21 17:29:19 +0800 | [diff] [blame] | 513 | #define CONFIG_SYS_PCI_64BIT |
| 514 | |
| 515 | #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 |
| 516 | #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ |
| 517 | #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 |
| 518 | #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ |
| 519 | |
| 520 | #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 |
| 521 | #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 |
| 522 | #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ |
| 523 | |
| 524 | #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 |
| 525 | #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 |
| 526 | #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ |
| 527 | |
| 528 | #ifdef CONFIG_PCI |
| 529 | #define CONFIG_NET_MULTI |
| 530 | #define CONFIG_PCI_PNP |
| 531 | #define CONFIG_E1000 |
| 532 | #define CONFIG_PCI_SCAN_SHOW |
| 533 | #define CONFIG_CMD_PCI |
| 534 | #define CONFIG_CMD_NET |
| 535 | #endif |
| 536 | |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 537 | #define CONFIG_CMD_PING |
| 538 | #define CONFIG_CMD_DHCP |
| 539 | #define CONFIG_CMD_MII |
| 540 | #define CONFIG_CMD_NET |
| 541 | |
| 542 | #define CONFIG_CMDLINE_TAG |
| 543 | #define CONFIG_CMDLINE_EDITING |
Alison Wang | 9da5178 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 544 | |
Alison Wang | 2145a37 | 2014-12-09 17:38:02 +0800 | [diff] [blame] | 545 | #ifdef CONFIG_QSPI_BOOT |
| 546 | #undef CONFIG_CMD_IMLS |
| 547 | #else |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 548 | #define CONFIG_CMD_IMLS |
Alison Wang | 2145a37 | 2014-12-09 17:38:02 +0800 | [diff] [blame] | 549 | #endif |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 550 | |
Xiubo Li | 563e3ce | 2014-11-21 17:40:57 +0800 | [diff] [blame] | 551 | #define CONFIG_ARMV7_NONSEC |
| 552 | #define CONFIG_ARMV7_VIRT |
| 553 | #define CONFIG_PEN_ADDR_BIG_ENDIAN |
Xiubo Li | 54de065 | 2014-11-21 17:40:58 +0800 | [diff] [blame] | 554 | #define CONFIG_LS102XA_NS_ACCESS |
Xiubo Li | 563e3ce | 2014-11-21 17:40:57 +0800 | [diff] [blame] | 555 | #define CONFIG_SMP_PEN_ADDR 0x01ee0200 |
| 556 | #define CONFIG_TIMER_CLK_FREQ 12500000 |
| 557 | #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR |
| 558 | |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 559 | #define CONFIG_HWCONFIG |
| 560 | #define HWCONFIG_BUFFER_SIZE 128 |
| 561 | |
| 562 | #define CONFIG_BOOTDELAY 3 |
| 563 | |
Zhao Qiang | 9fc2f30 | 2014-09-26 16:25:32 +0800 | [diff] [blame] | 564 | #define CONFIG_SYS_QE_FW_ADDR 0x67f40000 |
| 565 | |
Alison Wang | e2f33ae | 2015-01-04 15:30:58 +0800 | [diff] [blame] | 566 | #ifdef CONFIG_LPUART |
| 567 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 568 | "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ |
| 569 | "fdt_high=0xcfffffff\0" \ |
| 570 | "initrd_high=0xcfffffff\0" \ |
| 571 | "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" |
| 572 | #else |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 573 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 574 | "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ |
| 575 | "fdt_high=0xcfffffff\0" \ |
| 576 | "initrd_high=0xcfffffff\0" \ |
| 577 | "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" |
Alison Wang | e2f33ae | 2015-01-04 15:30:58 +0800 | [diff] [blame] | 578 | #endif |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 579 | |
| 580 | /* |
| 581 | * Miscellaneous configurable options |
| 582 | */ |
| 583 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 584 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
| 585 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 586 | #define CONFIG_AUTO_COMPLETE |
| 587 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 588 | #define CONFIG_SYS_PBSIZE \ |
| 589 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
| 590 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 591 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 592 | |
| 593 | #define CONFIG_CMD_ENV_EXISTS |
| 594 | #define CONFIG_CMD_GREPENV |
| 595 | #define CONFIG_CMD_MEMINFO |
| 596 | #define CONFIG_CMD_MEMTEST |
| 597 | #define CONFIG_SYS_MEMTEST_START 0x80000000 |
| 598 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff |
| 599 | |
| 600 | #define CONFIG_SYS_LOAD_ADDR 0x82000000 |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 601 | |
Xiubo Li | 03d40aa | 2014-11-21 17:40:59 +0800 | [diff] [blame] | 602 | #define CONFIG_LS102XA_STREAM_ID |
| 603 | |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 604 | /* |
| 605 | * Stack sizes |
| 606 | * The stack sizes are set up in start.S using the settings below |
| 607 | */ |
| 608 | #define CONFIG_STACKSIZE (30 * 1024) |
| 609 | |
| 610 | #define CONFIG_SYS_INIT_SP_OFFSET \ |
| 611 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 612 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 613 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
| 614 | |
Alison Wang | 9da5178 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 615 | #ifdef CONFIG_SPL_BUILD |
| 616 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE |
| 617 | #else |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 618 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
Alison Wang | 9da5178 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 619 | #endif |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 620 | |
| 621 | /* |
| 622 | * Environment |
| 623 | */ |
| 624 | #define CONFIG_ENV_OVERWRITE |
| 625 | |
Alison Wang | 9da5178 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 626 | #if defined(CONFIG_SD_BOOT) |
| 627 | #define CONFIG_ENV_OFFSET 0x100000 |
| 628 | #define CONFIG_ENV_IS_IN_MMC |
| 629 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 630 | #define CONFIG_ENV_SIZE 0x2000 |
Alison Wang | 2145a37 | 2014-12-09 17:38:02 +0800 | [diff] [blame] | 631 | #elif defined(CONFIG_QSPI_BOOT) |
| 632 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 633 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
| 634 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ |
| 635 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
Alison Wang | ab98bb5 | 2014-12-09 17:38:14 +0800 | [diff] [blame] | 636 | #elif defined(CONFIG_NAND_BOOT) |
| 637 | #define CONFIG_ENV_IS_IN_NAND |
| 638 | #define CONFIG_ENV_SIZE 0x2000 |
| 639 | #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) |
Alison Wang | 9da5178 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 640 | #else |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 641 | #define CONFIG_ENV_IS_IN_FLASH |
| 642 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
| 643 | #define CONFIG_ENV_SIZE 0x2000 |
| 644 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
Alison Wang | 9da5178 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 645 | #endif |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 646 | |
| 647 | #define CONFIG_OF_LIBFDT |
| 648 | #define CONFIG_OF_BOARD_SETUP |
| 649 | #define CONFIG_CMD_BOOTZ |
| 650 | |
Ruchika Gupta | 901ae76 | 2014-10-15 11:39:06 +0530 | [diff] [blame] | 651 | #define CONFIG_MISC_INIT_R |
| 652 | |
| 653 | /* Hash command with SHA acceleration supported in hardware */ |
| 654 | #define CONFIG_CMD_HASH |
| 655 | #define CONFIG_SHA_HW_ACCEL |
| 656 | |
Ruchika Gupta | 10be7d4 | 2014-10-07 15:48:47 +0530 | [diff] [blame] | 657 | #ifdef CONFIG_SECURE_BOOT |
| 658 | #define CONFIG_CMD_BLOB |
gaurav rana | f79323c | 2015-03-10 14:08:50 +0530 | [diff] [blame] | 659 | #include <asm/fsl_secure_boot.h> |
Ruchika Gupta | 10be7d4 | 2014-10-07 15:48:47 +0530 | [diff] [blame] | 660 | #endif |
| 661 | |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 662 | #endif |