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Mike Frysinger9771c0c2008-10-12 23:22:25 -04001/*
2 * U-boot - Configuration file for CSP Minotaur board
3 *
4 * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch>
5 * Minotaur config, brushed up for official uClinux dist.
6 * Parallel flash support disabled, SPI flash boot command
7 * added ('run flashboot').
8 *
9 * Flash image map:
10 *
11 * 0x00000000 u-boot bootstrap
12 * 0x00010000 environment
13 * 0x00020000 u-boot code
14 * 0x00030000 uImage.initramfs
15 *
16 */
17
18#ifndef __CONFIG_BF537_SRV1_H__
19#define __CONFIG_BF537_SRV1_H__
20
Mike Frysinger18a407c2009-04-24 17:22:40 -040021#include <asm/config-pre.h>
Mike Frysinger9771c0c2008-10-12 23:22:25 -040022
23
24/*
25 * Processor Settings
26 */
Mike Frysinger5b0c1282010-12-23 14:58:37 -050027#define CONFIG_BFIN_CPU bf537-0.2
Mike Frysinger9771c0c2008-10-12 23:22:25 -040028#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
29
30
31/*
32 * Clock Settings
33 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
34 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
35 */
36/* CONFIG_CLKIN_HZ is any value in Hz */
37#define CONFIG_CLKIN_HZ 22118400
38/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
39/* 1 = CLKIN / 2 */
40#define CONFIG_CLKIN_HALF 0
41/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
42/* 1 = bypass PLL */
43#define CONFIG_PLL_BYPASS 0
44/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
45/* Values can range from 0-63 (where 0 means 64) */
46#define CONFIG_VCO_MULT 20
47/* CCLK_DIV controls the core clock divider */
48/* Values can be 1, 2, 4, or 8 ONLY */
49#define CONFIG_CCLK_DIV 1
50/* SCLK_DIV controls the system clock divider */
51/* Values can range from 1-15 */
52#define CONFIG_SCLK_DIV 5
53
54
55/*
56 * Memory Settings
57 */
58#define CONFIG_MEM_SIZE 32
59#define CONFIG_MEM_ADD_WDTH 9
60
61#define CONFIG_EBIU_SDRRC_VAL 0x2ac
62#define CONFIG_EBIU_SDGCTL_VAL 0x91110d
63
64#define CONFIG_EBIU_AMGCTL_VAL 0xFF
65#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
66#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
67
68#define CONFIG_SYS_MONITOR_LEN (256 << 10)
69#define CONFIG_SYS_MALLOC_LEN (384 << 10)
70
71
72/*
73 * Network Settings
74 */
75#ifndef __ADSPBF534__
76#define CONFIG_BFIN_MAC
77#define CONFIG_NETCONSOLE 1
Mike Frysinger9771c0c2008-10-12 23:22:25 -040078#endif
79#ifdef CONFIG_BFIN_MAC
80#define CONFIG_IPADDR 192.168.0.15
81#define CONFIG_NETMASK 255.255.255.0
82#define CONFIG_GATEWAYIP 192.168.0.1
83#define CONFIG_SERVERIP 192.168.0.2
84#define CONFIG_HOSTNAME bf537-srv1
85#endif
86
87#define CONFIG_SYS_AUTOLOAD "no"
Joe Hershberger257ff782011-10-13 13:03:47 +000088#define CONFIG_ROOTPATH "/romfs"
Masahiro Yamada56300392014-04-18 19:09:49 +090089#define CONFIG_LIB_RAND
Mike Frysinger9771c0c2008-10-12 23:22:25 -040090
91/*
92 * Flash Settings
93 */
94/* We don't have a parallel flash chip there */
95#define CONFIG_SYS_NO_FLASH
96
97
98/*
99 * SPI Settings
100 */
101#define CONFIG_BFIN_SPI
102#define CONFIG_ENV_SPI_MAX_HZ 30000000
Mike Frysinger9a4406462009-06-14 22:29:35 -0400103#define CONFIG_SF_DEFAULT_SPEED 30000000
Mike Frysinger9771c0c2008-10-12 23:22:25 -0400104#define CONFIG_SPI_FLASH
105#define CONFIG_SPI_FLASH_STMICRO
106
107
108/*
109 * Env Storage Settings
110 */
111#define CONFIG_ENV_IS_IN_SPI_FLASH
112#define CONFIG_ENV_OFFSET 0x10000
113#define CONFIG_ENV_SIZE 0x10000
114#define CONFIG_ENV_SECT_SIZE 0x10000
Mike Frysinger45b57bd2009-07-21 22:17:36 -0400115#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Mike Frysinger9771c0c2008-10-12 23:22:25 -0400116
117
118/*
119 * I2C settings
120 */
Scott Jiang80d27fa2014-11-13 15:30:55 +0800121#define CONFIG_SYS_I2C
Scott Jiang655761e2014-11-13 15:30:53 +0800122#define CONFIG_SYS_I2C_ADI
Mike Frysinger9771c0c2008-10-12 23:22:25 -0400123#define CONFIG_SYS_I2C_SPEED 50000
124#define CONFIG_SYS_I2C_SLAVE 0
125
126
127/*
128 * Misc Settings
129 */
130#define CONFIG_SYS_LONGHELP 1
131#define CONFIG_CMDLINE_EDITING 1
132#define CONFIG_ENV_OVERWRITE 1
Mike Frysinger9771c0c2008-10-12 23:22:25 -0400133
134#define CONFIG_BAUDRATE 115200
135#define CONFIG_UART_CONSOLE 0
Sonic Zhangb9efd352013-11-18 14:50:19 +0800136#define CONFIG_BFIN_SERIAL
Mike Frysinger9771c0c2008-10-12 23:22:25 -0400137
138#define CONFIG_PANIC_HANG 1
139#define CONFIG_RTC_BFIN 1
140#define CONFIG_BOOT_RETRY_TIME -1
141#define CONFIG_LOADS_ECHO 1
142
143#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
144# define CONFIG_BOOTDELAY -1
145#else
146# define CONFIG_BOOTDELAY 5
147#endif
148
149#include <config_cmd_default.h>
150
151#ifdef CONFIG_BFIN_MAC
152# define CONFIG_CMD_DHCP
153# define CONFIG_CMD_PING
154#else
155# undef CONFIG_CMD_NET
Mike Frysinger688937d2010-12-22 23:26:08 -0500156# undef CONFIG_CMD_NFS
Mike Frysinger9771c0c2008-10-12 23:22:25 -0400157#endif
158
159#define CONFIG_CMD_BOOTLDR
160#define CONFIG_CMD_CACHE
161#define CONFIG_CMD_DATE
162#define CONFIG_CMD_ELF
163#undef CONFIG_CMD_FLASH
164#define CONFIG_CMD_I2C
165#undef CONFIG_CMD_IMLS
166#define CONFIG_CMD_SF
167
168#define CONFIG_BOOTCOMMAND "run flashboot"
169#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
170#define CONFIG_SYS_PROMPT "srv1> "
171
172#define BOOT_ENV_SETTINGS \
173 "update=tftpboot $(loadaddr) u-boot.ldr;" \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200174 "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
Mike Frysinger9771c0c2008-10-12 23:22:25 -0400175 "sf erase 0 0x30000;" \
176 "sf write $(loadaddr) 0 $(filesize)" \
177 "flashboot=sf read 0x1000000 0x30000 0x320000;" \
178 "bootm 0x1000000\0"
179#ifdef CONFIG_BFIN_MAC
180# define NETWORK_ENV_SETTINGS \
181 "nfsargs=setenv bootargs root=/dev/nfs rw " \
182 "nfsroot=$(serverip):$(rootpath)\0" \
183 "addip=setenv bootargs $(bootargs) " \
184 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
185 ":$(hostname):eth0:off\0" \
186 "ramboot=tftpboot $(loadaddr) linux;" \
187 "run ramargs;run addip;bootelf\0" \
188 "nfsboot=tftpboot $(loadaddr) linux;" \
189 "run nfsargs;run addip;bootelf\0"
190#else
191# define NETWORK_ENV_SETTINGS
192#endif
193#define CONFIG_EXTRA_ENV_SETTINGS \
194 NETWORK_ENV_SETTINGS \
195 "ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \
196 BOOT_ENV_SETTINGS
197
Mike Frysinger9771c0c2008-10-12 23:22:25 -0400198#endif