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Kumar Gala3ab0b2d2008-08-12 11:13:08 -05001/*
Kumar Galaa9db4ec2011-01-11 00:52:35 -06002 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
Kumar Gala3ab0b2d2008-08-12 11:13:08 -05003 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala3ab0b2d2008-08-12 11:13:08 -05005 */
6
7/*
8 * mpc8572ds board configuration file
9 *
10 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
York Sun4bd582d2014-04-30 14:43:49 -070014#define CONFIG_SYS_GENERIC_BOARD
15#define CONFIG_DISPLAY_BOARDINFO
16
Kumar Galaf6f382b2010-05-21 04:05:14 -050017#include "../board/freescale/common/ics307_clk.h"
18
Wolfgang Denkdc25d152010-10-04 19:58:00 +020019#ifdef CONFIG_36BIT
Kumar Gala0d899ab2009-09-10 16:23:45 -050020#define CONFIG_PHYS_64BIT
21#endif
22
Kumar Gala90a535b2010-11-12 08:22:01 -060023#ifndef CONFIG_SYS_TEXT_BASE
York Sun6f231f32014-04-25 12:06:17 -070024#define CONFIG_SYS_TEXT_BASE 0xeff40000
Kumar Gala90a535b2010-11-12 08:22:01 -060025#endif
26
Kumar Galae727a362011-01-12 02:48:53 -060027#ifndef CONFIG_RESET_VECTOR_ADDRESS
28#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
29#endif
30
Kumar Gala90a535b2010-11-12 08:22:01 -060031#ifndef CONFIG_SYS_MONITOR_BASE
32#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
33#endif
34
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050035/* High Level Configuration Options */
36#define CONFIG_BOOKE 1 /* BOOKE */
37#define CONFIG_E500 1 /* BOOKE e500 family */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050038#define CONFIG_MPC8572 1
39#define CONFIG_MPC8572DS 1
40#define CONFIG_MP 1 /* support multiple processors */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050041
Kumar Gala1a5ba5f2009-01-23 14:22:13 -060042#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050043#define CONFIG_PCI 1 /* Enable PCI/PCIE */
44#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
45#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
46#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
47#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhosb4458732013-05-30 07:06:12 +000048#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050049#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala7738d5c2008-10-21 11:33:58 -050050#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050051
52#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
53
54#define CONFIG_TSEC_ENET /* tsec ethernet support */
55#define CONFIG_ENV_OVERWRITE
56
Kumar Galaf6f382b2010-05-21 04:05:14 -050057#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
58#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
Haiying Wangbcf35e52008-10-03 12:37:41 -040059#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050060
61/*
62 * These can be toggled for performance analysis, otherwise use default.
63 */
64#define CONFIG_L2_CACHE /* toggle L2 cache */
65#define CONFIG_BTB /* toggle branch predition */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050066
67#define CONFIG_ENABLE_36BIT_PHYS 1
68
Kumar Galae0f97412009-01-23 14:22:14 -060069#ifdef CONFIG_PHYS_64BIT
70#define CONFIG_ADDR_MAP 1
71#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
72#endif
73
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020074#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
75#define CONFIG_SYS_MEMTEST_END 0x7fffffff
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050076#define CONFIG_PANIC_HANG /* do not reset board on panic */
77
78/*
Kumar Gala90a535b2010-11-12 08:22:01 -060079 * Config the L2 Cache as L2 SRAM
80 */
81#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
82#ifdef CONFIG_PHYS_64BIT
83#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
84#else
85#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
86#endif
87#define CONFIG_SYS_L2_SIZE (512 << 10)
88#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
89
Timur Tabid8f341c2011-08-04 18:03:41 -050090#define CONFIG_SYS_CCSRBAR 0xffe00000
91#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050092
Kumar Gala842aa5b2011-11-09 09:10:49 -060093#if defined(CONFIG_NAND_SPL)
Timur Tabid8f341c2011-08-04 18:03:41 -050094#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Kumar Gala90a535b2010-11-12 08:22:01 -060095#endif
96
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050097/* DDR Setup */
Kumar Gala6630ffb2009-02-06 09:56:35 -060098#define CONFIG_VERY_BIG_RAM
York Sunf0626592013-09-30 09:22:09 -070099#define CONFIG_SYS_FSL_DDR2
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500100#undef CONFIG_FSL_DDR_INTERACTIVE
101#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
102#define CONFIG_DDR_SPD
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500103
York Sun5e8435a2011-01-25 21:51:29 -0800104#define CONFIG_DDR_ECC
Dave Liud3ca1242008-10-28 17:53:38 +0800105#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500106#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
107
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200108#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
109#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500110
111#define CONFIG_NUM_DDR_CONTROLLERS 2
112#define CONFIG_DIMM_SLOTS_PER_CTLR 1
113#define CONFIG_CHIP_SELECTS_PER_CTRL 2
114
115/* I2C addresses of SPD EEPROMs */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500117#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
118#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
119
120/* These are used when DDR doesn't use SPD. */
Dave Liu6b78b162008-11-28 20:16:58 +0800121#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
122#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
123#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
124#define CONFIG_SYS_DDR_TIMING_3 0x00020000
125#define CONFIG_SYS_DDR_TIMING_0 0x00260802
126#define CONFIG_SYS_DDR_TIMING_1 0x626b2634
127#define CONFIG_SYS_DDR_TIMING_2 0x062874cf
128#define CONFIG_SYS_DDR_MODE_1 0x00440462
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#define CONFIG_SYS_DDR_MODE_2 0x00000000
Dave Liu6b78b162008-11-28 20:16:58 +0800130#define CONFIG_SYS_DDR_INTERVAL 0x0c300100
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200131#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
Dave Liu6b78b162008-11-28 20:16:58 +0800132#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
133#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200134#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
Dave Liu6b78b162008-11-28 20:16:58 +0800135#define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
136#define CONFIG_SYS_DDR_CONTROL2 0x24400000
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500137
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200138#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
139#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
140#define CONFIG_SYS_DDR_SBE 0x00010000
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500141
142/*
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500143 * Make sure required options are set
144 */
145#ifndef CONFIG_SPD_EEPROM
146#error ("CONFIG_SPD_EEPROM is required")
147#endif
148
149#undef CONFIG_CLOCKS_IN_MHZ
150
151/*
152 * Memory map
153 *
154 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
155 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
156 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
157 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
158 *
159 * Localbus cacheable (TBD)
160 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
161 *
162 * Localbus non-cacheable
163 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
164 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100165 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500166 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
167 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
168 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
169 */
170
171/*
172 * Local Bus Definitions
173 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200174#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
Kumar Galae0f97412009-01-23 14:22:14 -0600175#ifdef CONFIG_PHYS_64BIT
176#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
177#else
Kumar Gala4be8b572008-12-02 14:19:34 -0600178#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
Kumar Galae0f97412009-01-23 14:22:14 -0600179#endif
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500180
Kumar Gala90a535b2010-11-12 08:22:01 -0600181
182#define CONFIG_FLASH_BR_PRELIM \
Timur Tabib56570c2012-07-06 07:39:26 +0000183 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
Kumar Gala90a535b2010-11-12 08:22:01 -0600184#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500185
Kumar Gala4be8b572008-12-02 14:19:34 -0600186#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
187#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500188
Kumar Galae0f97412009-01-23 14:22:14 -0600189#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200190#define CONFIG_SYS_FLASH_QUIET_TEST
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500191#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
192
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200193#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
194#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
195#undef CONFIG_SYS_FLASH_CHECKSUM
196#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
197#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500198
Kumar Gala90a535b2010-11-12 08:22:01 -0600199#undef CONFIG_SYS_RAMBOOT
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500200
201#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202#define CONFIG_SYS_FLASH_CFI
203#define CONFIG_SYS_FLASH_EMPTY_INFO
204#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500205
206#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
207
Kumar Gala362b9982010-11-19 08:53:25 -0600208#define CONFIG_HWCONFIG /* enable hwconfig */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500209#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
210#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Kumar Galae0f97412009-01-23 14:22:14 -0600211#ifdef CONFIG_PHYS_64BIT
212#define PIXIS_BASE_PHYS 0xfffdf0000ull
213#else
Kumar Gala0f492b42008-12-02 14:19:33 -0600214#define PIXIS_BASE_PHYS PIXIS_BASE
Kumar Galae0f97412009-01-23 14:22:14 -0600215#endif
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500216
Kumar Gala0f492b42008-12-02 14:19:33 -0600217#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200218#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500219
220#define PIXIS_ID 0x0 /* Board ID at offset 0 */
221#define PIXIS_VER 0x1 /* Board version at offset 1 */
222#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
223#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
224#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
225#define PIXIS_PWR 0x5 /* PIXIS Power status register */
226#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
227#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
228#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
229#define PIXIS_VCTL 0x10 /* VELA Control Register */
230#define PIXIS_VSTAT 0x11 /* VELA Status Register */
231#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
232#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
233#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
234#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Galae21db032009-07-14 22:42:01 -0500235#define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
236#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
237#define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
238#define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
239#define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500240#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
241#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
242#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
243#define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
244#define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
245#define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
246#define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
247#define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
248#define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
249#define PIXIS_VWATCH 0x24 /* Watchdog Register */
250#define PIXIS_LED 0x25 /* LED Register */
251
Kumar Gala90a535b2010-11-12 08:22:01 -0600252#define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */
253
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500254/* old pixis referenced names */
255#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
256#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200257#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
Liu Yuc49bce42008-10-10 11:40:59 +0800258#define PIXIS_VSPEED2_TSEC1SER 0x8
259#define PIXIS_VSPEED2_TSEC2SER 0x4
260#define PIXIS_VSPEED2_TSEC3SER 0x2
261#define PIXIS_VSPEED2_TSEC4SER 0x1
262#define PIXIS_VCFGEN1_TSEC1SER 0x20
263#define PIXIS_VCFGEN1_TSEC2SER 0x20
264#define PIXIS_VCFGEN1_TSEC3SER 0x20
265#define PIXIS_VCFGEN1_TSEC4SER 0x20
266#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
267 | PIXIS_VSPEED2_TSEC2SER \
268 | PIXIS_VSPEED2_TSEC3SER \
269 | PIXIS_VSPEED2_TSEC4SER)
270#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
271 | PIXIS_VCFGEN1_TSEC2SER \
272 | PIXIS_VCFGEN1_TSEC3SER \
273 | PIXIS_VCFGEN1_TSEC4SER)
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500274
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200275#define CONFIG_SYS_INIT_RAM_LOCK 1
276#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200277#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500278
Wolfgang Denk0191e472010-10-26 14:34:52 +0200279#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200280#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500281
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200282#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
283#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500284
Kumar Gala90a535b2010-11-12 08:22:01 -0600285#ifndef CONFIG_NAND_SPL
Haiying Wang9fce13f2008-10-29 13:32:59 -0400286#define CONFIG_SYS_NAND_BASE 0xffa00000
Kumar Galae0f97412009-01-23 14:22:14 -0600287#ifdef CONFIG_PHYS_64BIT
288#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
289#else
Haiying Wang9fce13f2008-10-29 13:32:59 -0400290#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
Kumar Galae0f97412009-01-23 14:22:14 -0600291#endif
Kumar Gala90a535b2010-11-12 08:22:01 -0600292#else
293#define CONFIG_SYS_NAND_BASE 0xfff00000
294#ifdef CONFIG_PHYS_64BIT
295#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
296#else
297#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
298#endif
299#endif
300
Haiying Wang9fce13f2008-10-29 13:32:59 -0400301#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
302 CONFIG_SYS_NAND_BASE + 0x40000, \
303 CONFIG_SYS_NAND_BASE + 0x80000,\
304 CONFIG_SYS_NAND_BASE + 0xC0000}
305#define CONFIG_SYS_MAX_NAND_DEVICE 4
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100306#define CONFIG_CMD_NAND 1
307#define CONFIG_NAND_FSL_ELBC 1
Haiying Wang9fce13f2008-10-29 13:32:59 -0400308#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
Prabhakar Kushwaha4d2ba172013-10-04 13:47:58 +0530309#define CONFIG_SYS_NAND_MAX_OOBFREE 5
310#define CONFIG_SYS_NAND_MAX_ECCPOS 56
Haiying Wang9fce13f2008-10-29 13:32:59 -0400311
Kumar Gala90a535b2010-11-12 08:22:01 -0600312/* NAND boot: 4K NAND loader config */
313#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
314#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
315#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
316#define CONFIG_SYS_NAND_U_BOOT_START \
317 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
318#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
319#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
320#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
321
322
Haiying Wang9fce13f2008-10-29 13:32:59 -0400323/* NAND flash config */
Matthew McClintock48aab142011-04-05 14:39:33 -0500324#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100325 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
326 | BR_PS_8 /* Port Size = 8 bit */ \
327 | BR_MS_FCM /* MSEL = FCM */ \
328 | BR_V) /* valid */
Matthew McClintock48aab142011-04-05 14:39:33 -0500329#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100330 | OR_FCM_PGS /* Large Page*/ \
331 | OR_FCM_CSCT \
332 | OR_FCM_CST \
333 | OR_FCM_CHT \
334 | OR_FCM_SCY_1 \
335 | OR_FCM_TRLX \
336 | OR_FCM_EHTR)
Haiying Wang9fce13f2008-10-29 13:32:59 -0400337
Kumar Gala90a535b2010-11-12 08:22:01 -0600338#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
339#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintock48aab142011-04-05 14:39:33 -0500340#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
341#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Timur Tabib56570c2012-07-06 07:39:26 +0000342#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100343 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
344 | BR_PS_8 /* Port Size = 8 bit */ \
345 | BR_MS_FCM /* MSEL = FCM */ \
346 | BR_V) /* valid */
Matthew McClintock48aab142011-04-05 14:39:33 -0500347#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Timur Tabib56570c2012-07-06 07:39:26 +0000348#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100349 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
350 | BR_PS_8 /* Port Size = 8 bit */ \
351 | BR_MS_FCM /* MSEL = FCM */ \
352 | BR_V) /* valid */
Matthew McClintock48aab142011-04-05 14:39:33 -0500353#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Haiying Wang9fce13f2008-10-29 13:32:59 -0400354
Timur Tabib56570c2012-07-06 07:39:26 +0000355#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100356 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
357 | BR_PS_8 /* Port Size = 8 bit */ \
358 | BR_MS_FCM /* MSEL = FCM */ \
359 | BR_V) /* valid */
Matthew McClintock48aab142011-04-05 14:39:33 -0500360#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Haiying Wang9fce13f2008-10-29 13:32:59 -0400361
362
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500363/* Serial Port - controlled on board with jumper J8
364 * open - index 2
365 * shorted - index 1
366 */
367#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200368#define CONFIG_SYS_NS16550
369#define CONFIG_SYS_NS16550_SERIAL
370#define CONFIG_SYS_NS16550_REG_SIZE 1
371#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Gala90a535b2010-11-12 08:22:01 -0600372#ifdef CONFIG_NAND_SPL
373#define CONFIG_NS16550_MIN_FUNCTIONS
374#endif
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500375
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200376#define CONFIG_SYS_BAUDRATE_TABLE \
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500377 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
378
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200379#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
380#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500381
382/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200383#define CONFIG_SYS_HUSH_PARSER
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500384
385/*
386 * Pass open firmware flat tree
387 */
388#define CONFIG_OF_LIBFDT 1
389#define CONFIG_OF_BOARD_SETUP 1
390#define CONFIG_OF_STDOUT_VIA_ALIAS 1
391
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500392/* new uImage format support */
393#define CONFIG_FIT 1
394#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
395
396/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +0200397#define CONFIG_SYS_I2C
398#define CONFIG_SYS_I2C_FSL
399#define CONFIG_SYS_FSL_I2C_SPEED 400000
400#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
401#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
402#define CONFIG_SYS_FSL_I2C2_SPEED 400000
403#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
404#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
405#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200406#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500407
408/*
Haiying Wang374130f2008-10-03 11:47:30 -0400409 * I2C2 EEPROM
410 */
411#define CONFIG_ID_EEPROM
412#ifdef CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200413#define CONFIG_SYS_I2C_EEPROM_NXID
Haiying Wang374130f2008-10-03 11:47:30 -0400414#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200415#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
416#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
417#define CONFIG_SYS_EEPROM_BUS_NUM 1
Haiying Wang374130f2008-10-03 11:47:30 -0400418
419/*
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500420 * General PCI
421 * Memory space is mapped 1-1, but I/O space must start from 0.
422 */
423
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500424/* controller 3, direct to uli, tgtid 3, Base address 8000 */
Kumar Galad165dc52010-12-17 06:53:52 -0600425#define CONFIG_SYS_PCIE3_NAME "ULI"
Kumar Galaef43b6e2008-12-02 16:08:39 -0600426#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
Kumar Galae0f97412009-01-23 14:22:14 -0600427#ifdef CONFIG_PHYS_64BIT
Kumar Galae1cb3db2009-06-18 08:39:42 -0500428#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600429#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
430#else
Kumar Gala2275d0e2009-02-09 22:03:05 -0600431#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600432#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
Kumar Galae0f97412009-01-23 14:22:14 -0600433#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200434#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600435#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600436#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Kumar Galae0f97412009-01-23 14:22:14 -0600437#ifdef CONFIG_PHYS_64BIT
438#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
439#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200440#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
Kumar Galae0f97412009-01-23 14:22:14 -0600441#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200442#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500443
444/* controller 2, Slot 2, tgtid 2, Base address 9000 */
Kumar Galad165dc52010-12-17 06:53:52 -0600445#define CONFIG_SYS_PCIE2_NAME "Slot 1"
Kumar Galaef43b6e2008-12-02 16:08:39 -0600446#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600447#ifdef CONFIG_PHYS_64BIT
Kumar Galae1cb3db2009-06-18 08:39:42 -0500448#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600449#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
450#else
Kumar Gala2275d0e2009-02-09 22:03:05 -0600451#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600452#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600453#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200454#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600455#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600456#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Kumar Galae0f97412009-01-23 14:22:14 -0600457#ifdef CONFIG_PHYS_64BIT
458#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
459#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200460#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
Kumar Galae0f97412009-01-23 14:22:14 -0600461#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200462#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500463
464/* controller 1, Slot 1, tgtid 1, Base address a000 */
Kumar Galad165dc52010-12-17 06:53:52 -0600465#define CONFIG_SYS_PCIE1_NAME "Slot 2"
Kumar Galaef43b6e2008-12-02 16:08:39 -0600466#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600467#ifdef CONFIG_PHYS_64BIT
Kumar Galae1cb3db2009-06-18 08:39:42 -0500468#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600469#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
470#else
Kumar Gala2275d0e2009-02-09 22:03:05 -0600471#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600472#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
Kumar Galae0f97412009-01-23 14:22:14 -0600473#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200474#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600475#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600476#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Kumar Galae0f97412009-01-23 14:22:14 -0600477#ifdef CONFIG_PHYS_64BIT
478#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
479#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200480#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
Kumar Galae0f97412009-01-23 14:22:14 -0600481#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200482#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500483
484#if defined(CONFIG_PCI)
485
486/*PCIE video card used*/
Kumar Gala60ff4642008-12-02 16:08:40 -0600487#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500488
489/* video */
490#define CONFIG_VIDEO
491
492#if defined(CONFIG_VIDEO)
493#define CONFIG_BIOSEMU
494#define CONFIG_CFB_CONSOLE
495#define CONFIG_VIDEO_SW_CURSOR
496#define CONFIG_VGA_AS_SINGLE_DEVICE
497#define CONFIG_ATI_RADEON_FB
498#define CONFIG_VIDEO_LOGO
499/*#define CONFIG_CONSOLE_CURSOR*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200500#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500501#endif
502
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500503#define CONFIG_PCI_PNP /* do pci plug-and-play */
504
505#undef CONFIG_EEPRO100
506#undef CONFIG_TULIP
507#undef CONFIG_RTL8139
Kumar Galacfc113e2010-11-09 23:19:50 -0600508#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500509
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500510#ifndef CONFIG_PCI_PNP
Kumar Gala64bb6d12008-12-02 16:08:37 -0600511 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
512 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500513 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
514#endif
515
516#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
517#define CONFIG_DOS_PARTITION
518#define CONFIG_SCSI_AHCI
519
520#ifdef CONFIG_SCSI_AHCI
Rob Herring83f66482013-08-24 10:10:54 -0500521#define CONFIG_LIBATA
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500522#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200523#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
524#define CONFIG_SYS_SCSI_MAX_LUN 1
525#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
526#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500527#endif /* SCSI */
528
529#endif /* CONFIG_PCI */
530
531
532#if defined(CONFIG_TSEC_ENET)
533
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500534#define CONFIG_MII 1 /* MII PHY management */
535#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
536#define CONFIG_TSEC1 1
537#define CONFIG_TSEC1_NAME "eTSEC1"
538#define CONFIG_TSEC2 1
539#define CONFIG_TSEC2_NAME "eTSEC2"
540#define CONFIG_TSEC3 1
541#define CONFIG_TSEC3_NAME "eTSEC3"
542#define CONFIG_TSEC4 1
543#define CONFIG_TSEC4_NAME "eTSEC4"
544
Liu Yuc49bce42008-10-10 11:40:59 +0800545#define CONFIG_PIXIS_SGMII_CMD
546#define CONFIG_FSL_SGMII_RISER 1
547#define SGMII_RISER_PHY_OFFSET 0x1c
548
549#ifdef CONFIG_FSL_SGMII_RISER
550#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
551#endif
552
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500553#define TSEC1_PHY_ADDR 0
554#define TSEC2_PHY_ADDR 1
555#define TSEC3_PHY_ADDR 2
556#define TSEC4_PHY_ADDR 3
557
558#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
559#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
560#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
561#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
562
563#define TSEC1_PHYIDX 0
564#define TSEC2_PHYIDX 0
565#define TSEC3_PHYIDX 0
566#define TSEC4_PHYIDX 0
567
568#define CONFIG_ETHPRIME "eTSEC1"
569
570#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
571#endif /* CONFIG_TSEC_ENET */
572
573/*
574 * Environment
575 */
Kumar Gala90a535b2010-11-12 08:22:01 -0600576
577#if defined(CONFIG_SYS_RAMBOOT)
Kumar Gala90a535b2010-11-12 08:22:01 -0600578
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500579#else
Kumar Gala90a535b2010-11-12 08:22:01 -0600580 #define CONFIG_ENV_IS_IN_FLASH 1
581 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
582 #define CONFIG_ENV_ADDR 0xfff80000
583 #else
584 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
585 #endif
586 #define CONFIG_ENV_SIZE 0x2000
587 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500588#endif
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500589
590#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200591#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500592
593/*
594 * Command line configuration.
595 */
596#include <config_cmd_default.h>
597
York Sun6cad41c2011-01-26 00:14:57 -0600598#define CONFIG_CMD_ERRATA
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500599#define CONFIG_CMD_IRQ
600#define CONFIG_CMD_PING
601#define CONFIG_CMD_I2C
602#define CONFIG_CMD_MII
603#define CONFIG_CMD_ELF
Kumar Gala489675d2008-09-22 23:40:42 -0500604#define CONFIG_CMD_SETEXPR
Becky Bruceee888da2010-06-17 11:37:25 -0500605#define CONFIG_CMD_REGINFO
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500606
607#if defined(CONFIG_PCI)
608#define CONFIG_CMD_PCI
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500609#define CONFIG_CMD_NET
610#define CONFIG_CMD_SCSI
611#define CONFIG_CMD_EXT2
612#endif
613
Zhao Chenhui36f15a82011-03-04 16:31:41 +0800614/*
615 * USB
616 */
617#define CONFIG_USB_EHCI
618
619#ifdef CONFIG_USB_EHCI
620#define CONFIG_CMD_USB
621#define CONFIG_USB_EHCI_PCI
622#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
623#define CONFIG_USB_STORAGE
624#define CONFIG_PCI_EHCI_DEVICE 0
625#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
626#endif
627
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500628#undef CONFIG_WATCHDOG /* watchdog disabled */
629
630/*
631 * Miscellaneous configurable options
632 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200633#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillipsf7758c12010-07-14 19:47:18 -0500634#define CONFIG_CMDLINE_EDITING /* Command-line editing */
635#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200636#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500637#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200638#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500639#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200640#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500641#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200642#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
643#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
644#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500645
646/*
647 * For booting Linux, the board info and command line data
Kumar Gala39ffcc12011-04-28 10:13:41 -0500648 * have to be in the first 64 MB of memory, since this is
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500649 * the maximum mapped by the Linux kernel during initialization.
650 */
Kumar Gala39ffcc12011-04-28 10:13:41 -0500651#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
652#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500653
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500654#if defined(CONFIG_CMD_KGDB)
655#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500656#endif
657
658/*
659 * Environment Configuration
660 */
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500661#if defined(CONFIG_TSEC_ENET)
662#define CONFIG_HAS_ETH0
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500663#define CONFIG_HAS_ETH1
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500664#define CONFIG_HAS_ETH2
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500665#define CONFIG_HAS_ETH3
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500666#endif
667
668#define CONFIG_IPADDR 192.168.1.254
669
670#define CONFIG_HOSTNAME unknown
Joe Hershberger257ff782011-10-13 13:03:47 +0000671#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000672#define CONFIG_BOOTFILE "uImage"
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500673#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
674
675#define CONFIG_SERVERIP 192.168.1.1
676#define CONFIG_GATEWAYIP 192.168.1.1
677#define CONFIG_NETMASK 255.255.255.0
678
679/* default location for tftp and bootm */
680#define CONFIG_LOADADDR 1000000
681
682#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
683#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
684
685#define CONFIG_BAUDRATE 115200
686
687#define CONFIG_EXTRA_ENV_SETTINGS \
Hongtao Jia39bb2f22012-12-20 19:36:12 +0000688"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200689"netdev=eth0\0" \
690"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
691"tftpflash=tftpboot $loadaddr $uboot; " \
692 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
693 " +$filesize; " \
694 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
695 " +$filesize; " \
696 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
697 " $filesize; " \
698 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
699 " +$filesize; " \
700 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
701 " $filesize\0" \
702"consoledev=ttyS0\0" \
703"ramdiskaddr=2000000\0" \
704"ramdiskfile=8572ds/ramdisk.uboot\0" \
705"fdtaddr=c00000\0" \
706"fdtfile=8572ds/mpc8572ds.dtb\0" \
707"bdev=sda3\0"
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500708
709#define CONFIG_HDBOOT \
710 "setenv bootargs root=/dev/$bdev rw " \
711 "console=$consoledev,$baudrate $othbootargs;" \
712 "tftp $loadaddr $bootfile;" \
713 "tftp $fdtaddr $fdtfile;" \
714 "bootm $loadaddr - $fdtaddr"
715
716#define CONFIG_NFSBOOTCOMMAND \
717 "setenv bootargs root=/dev/nfs rw " \
718 "nfsroot=$serverip:$rootpath " \
719 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
720 "console=$consoledev,$baudrate $othbootargs;" \
721 "tftp $loadaddr $bootfile;" \
722 "tftp $fdtaddr $fdtfile;" \
723 "bootm $loadaddr - $fdtaddr"
724
725#define CONFIG_RAMBOOTCOMMAND \
726 "setenv bootargs root=/dev/ram rw " \
727 "console=$consoledev,$baudrate $othbootargs;" \
728 "tftp $ramdiskaddr $ramdiskfile;" \
729 "tftp $loadaddr $bootfile;" \
730 "tftp $fdtaddr $fdtfile;" \
731 "bootm $loadaddr $ramdiskaddr $fdtaddr"
732
733#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
734
735#endif /* __CONFIG_H */