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wdenkaffae2b2002-08-17 09:36:01 +00001/*
2 * (C) Copyright 2001
3 * Denis Peter MPL AG Switzerland. d.peter@mpl.ch
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkaffae2b2002-08-17 09:36:01 +00006 */
7
8/*
9 * Date & Time support for the MC146818 (PIXX4) RTC
10 */
11
12/*#define DEBUG*/
13
14#include <common.h>
15#include <command.h>
16#include <rtc.h>
17
Paul Burtonc028f9b2013-11-08 11:18:55 +000018#if defined(__I386__) || defined(CONFIG_MALTA)
Graeme Russb87c30f2011-02-12 15:11:43 +110019#include <asm/io.h>
20#define in8(p) inb(p)
21#define out8(p, v) outb(v, p)
22#endif
23
Michal Simekc3e6c552008-07-14 19:45:37 +020024#if defined(CONFIG_CMD_DATE)
wdenkaffae2b2002-08-17 09:36:01 +000025
Simon Glass538059d2014-11-14 18:18:26 -070026/* Set this to 1 to clear the CMOS RAM */
27#define CLEAR_CMOS 0
28
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020029#define RTC_PORT_MC146818 CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x70
Wolfgang Denka1be4762008-05-20 16:00:29 +020030#define RTC_SECONDS 0x00
31#define RTC_SECONDS_ALARM 0x01
32#define RTC_MINUTES 0x02
33#define RTC_MINUTES_ALARM 0x03
34#define RTC_HOURS 0x04
35#define RTC_HOURS_ALARM 0x05
36#define RTC_DAY_OF_WEEK 0x06
37#define RTC_DATE_OF_MONTH 0x07
38#define RTC_MONTH 0x08
39#define RTC_YEAR 0x09
40#define RTC_CONFIG_A 0x0A
41#define RTC_CONFIG_B 0x0B
42#define RTC_CONFIG_C 0x0C
43#define RTC_CONFIG_D 0x0D
Simon Glass538059d2014-11-14 18:18:26 -070044#define RTC_REG_SIZE 0x80
45
46#define RTC_CONFIG_A_REF_CLCK_32KHZ (1 << 5)
47#define RTC_CONFIG_A_RATE_1024HZ 6
wdenkaffae2b2002-08-17 09:36:01 +000048
Simon Glass538059d2014-11-14 18:18:26 -070049#define RTC_CONFIG_B_24H (1 << 1)
50
51#define RTC_CONFIG_D_VALID_RAM_AND_TIME 0x80
wdenkaffae2b2002-08-17 09:36:01 +000052
53/* ------------------------------------------------------------------------- */
54
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030055int rtc_get (struct rtc_time *tmp)
wdenkaffae2b2002-08-17 09:36:01 +000056{
57 uchar sec, min, hour, mday, wday, mon, year;
58 /* here check if rtc can be accessed */
Simon Glassb4ae6002015-01-19 22:16:10 -070059 while ((rtc_read8(RTC_CONFIG_A) & 0x80) == 0x80);
60 sec = rtc_read8(RTC_SECONDS);
61 min = rtc_read8(RTC_MINUTES);
62 hour = rtc_read8(RTC_HOURS);
63 mday = rtc_read8(RTC_DATE_OF_MONTH);
64 wday = rtc_read8(RTC_DAY_OF_WEEK);
65 mon = rtc_read8(RTC_MONTH);
66 year = rtc_read8(RTC_YEAR);
wdenkaffae2b2002-08-17 09:36:01 +000067#ifdef RTC_DEBUG
68 printf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
69 "hr: %02x min: %02x sec: %02x\n",
wdenk452cfd62002-11-19 11:04:11 +000070 year, mon, mday, wday,
wdenkaffae2b2002-08-17 09:36:01 +000071 hour, min, sec );
72 printf ( "Alarms: month: %02x hour: %02x min: %02x sec: %02x\n",
Simon Glassb4ae6002015-01-19 22:16:10 -070073 rtc_read8(RTC_CONFIG_D) & 0x3F,
74 rtc_read8(RTC_HOURS_ALARM),
75 rtc_read8(RTC_MINUTES_ALARM),
76 rtc_read8(RTC_SECONDS_ALARM));
wdenkaffae2b2002-08-17 09:36:01 +000077#endif
78 tmp->tm_sec = bcd2bin (sec & 0x7F);
79 tmp->tm_min = bcd2bin (min & 0x7F);
80 tmp->tm_hour = bcd2bin (hour & 0x3F);
81 tmp->tm_mday = bcd2bin (mday & 0x3F);
82 tmp->tm_mon = bcd2bin (mon & 0x1F);
83 tmp->tm_year = bcd2bin (year);
84 tmp->tm_wday = bcd2bin (wday & 0x07);
85 if(tmp->tm_year<70)
86 tmp->tm_year+=2000;
87 else
88 tmp->tm_year+=1900;
89 tmp->tm_yday = 0;
90 tmp->tm_isdst= 0;
91#ifdef RTC_DEBUG
92 printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
93 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
94 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
95#endif
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030096
97 return 0;
wdenkaffae2b2002-08-17 09:36:01 +000098}
99
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200100int rtc_set (struct rtc_time *tmp)
wdenkaffae2b2002-08-17 09:36:01 +0000101{
102#ifdef RTC_DEBUG
103 printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
104 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
105 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
106#endif
Simon Glassb4ae6002015-01-19 22:16:10 -0700107 rtc_write8(RTC_CONFIG_B, 0x82); /* disable the RTC to update the regs */
wdenkaffae2b2002-08-17 09:36:01 +0000108
Simon Glassb4ae6002015-01-19 22:16:10 -0700109 rtc_write8(RTC_YEAR, bin2bcd(tmp->tm_year % 100));
110 rtc_write8(RTC_MONTH, bin2bcd(tmp->tm_mon));
111 rtc_write8(RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday));
112 rtc_write8(RTC_DATE_OF_MONTH, bin2bcd(tmp->tm_mday));
113 rtc_write8(RTC_HOURS, bin2bcd(tmp->tm_hour));
114 rtc_write8(RTC_MINUTES, bin2bcd(tmp->tm_min));
115 rtc_write8(RTC_SECONDS, bin2bcd(tmp->tm_sec));
116 rtc_write8(RTC_CONFIG_B, 0x02); /* enable the RTC to update the regs */
wdenkaffae2b2002-08-17 09:36:01 +0000117
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200118 return 0;
wdenkaffae2b2002-08-17 09:36:01 +0000119}
120
121void rtc_reset (void)
122{
Simon Glassb4ae6002015-01-19 22:16:10 -0700123 rtc_write8(RTC_CONFIG_B, 0x82); /* disable the RTC to update the regs */
124 rtc_write8(RTC_CONFIG_A, 0x20); /* Normal OP */
125 rtc_write8(RTC_CONFIG_B, 0x00);
126 rtc_write8(RTC_CONFIG_B, 0x00);
127 rtc_write8(RTC_CONFIG_B, 0x02); /* enable the RTC to update the regs */
wdenkaffae2b2002-08-17 09:36:01 +0000128}
129
130/* ------------------------------------------------------------------------- */
131
wdenkaffae2b2002-08-17 09:36:01 +0000132/*
133 * use direct memory access
134 */
Simon Glassb4ae6002015-01-19 22:16:10 -0700135int rtc_read8(int reg)
wdenkaffae2b2002-08-17 09:36:01 +0000136{
Simon Glassb4ae6002015-01-19 22:16:10 -0700137#ifdef CONFIG_SYS_RTC_REG_BASE_ADDR
Simon Glass538059d2014-11-14 18:18:26 -0700138 return in8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg);
Simon Glassb4ae6002015-01-19 22:16:10 -0700139#else
140 int ofs = 0;
141
142 if (reg >= 128) {
143 ofs = 2;
144 reg -= 128;
145 }
146 out8(RTC_PORT_MC146818 + ofs, reg);
147
148 return in8(RTC_PORT_MC146818 + ofs + 1);
149#endif
wdenkaffae2b2002-08-17 09:36:01 +0000150}
151
Simon Glassb4ae6002015-01-19 22:16:10 -0700152void rtc_write8(int reg, uchar val)
wdenkaffae2b2002-08-17 09:36:01 +0000153{
Simon Glassb4ae6002015-01-19 22:16:10 -0700154#ifdef CONFIG_SYS_RTC_REG_BASE_ADDR
Simon Glass538059d2014-11-14 18:18:26 -0700155 out8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg, val);
wdenkaffae2b2002-08-17 09:36:01 +0000156#else
Simon Glassb4ae6002015-01-19 22:16:10 -0700157 int ofs = 0;
158
159 if (reg >= 128) {
160 ofs = 2;
161 reg -= 128;
162 }
163 out8(RTC_PORT_MC146818 + ofs, reg);
164 out8(RTC_PORT_MC146818 + ofs + 1, val);
165#endif
166}
167
168u32 rtc_read32(int reg)
wdenkaffae2b2002-08-17 09:36:01 +0000169{
Simon Glassb4ae6002015-01-19 22:16:10 -0700170 u32 value = 0;
171 int i;
172
173 for (i = 0; i < sizeof(value); i++)
174 value |= rtc_read8(reg + i) << (i << 3);
175
176 return value;
wdenkaffae2b2002-08-17 09:36:01 +0000177}
178
Simon Glassb4ae6002015-01-19 22:16:10 -0700179void rtc_write32(int reg, u32 value)
wdenkaffae2b2002-08-17 09:36:01 +0000180{
Simon Glassb4ae6002015-01-19 22:16:10 -0700181 int i;
182
183 for (i = 0; i < sizeof(value); i++)
184 rtc_write8(reg + i, (value >> (i << 3)) & 0xff);
wdenkaffae2b2002-08-17 09:36:01 +0000185}
wdenkaffae2b2002-08-17 09:36:01 +0000186
Simon Glass538059d2014-11-14 18:18:26 -0700187void rtc_init(void)
188{
189#if CLEAR_CMOS
190 int i;
191
Simon Glassb4ae6002015-01-19 22:16:10 -0700192 rtc_write8(RTC_SECONDS_ALARM, 0);
193 rtc_write8(RTC_MINUTES_ALARM, 0);
194 rtc_write8(RTC_HOURS_ALARM, 0);
Simon Glass538059d2014-11-14 18:18:26 -0700195 for (i = RTC_CONFIG_A; i < RTC_REG_SIZE; i++)
Simon Glassb4ae6002015-01-19 22:16:10 -0700196 rtc_write8(i, 0);
Simon Glass538059d2014-11-14 18:18:26 -0700197 printf("RTC: zeroing CMOS RAM\n");
198#endif
199
200 /* Setup the real time clock */
Simon Glassb4ae6002015-01-19 22:16:10 -0700201 rtc_write8(RTC_CONFIG_B, RTC_CONFIG_B_24H);
Simon Glass538059d2014-11-14 18:18:26 -0700202 /* Setup the frequency it operates at */
Simon Glassb4ae6002015-01-19 22:16:10 -0700203 rtc_write8(RTC_CONFIG_A, RTC_CONFIG_A_REF_CLCK_32KHZ |
Simon Glass538059d2014-11-14 18:18:26 -0700204 RTC_CONFIG_A_RATE_1024HZ);
205 /* Ensure all reserved bits are 0 in register D */
Simon Glassb4ae6002015-01-19 22:16:10 -0700206 rtc_write8(RTC_CONFIG_D, RTC_CONFIG_D_VALID_RAM_AND_TIME);
Simon Glass538059d2014-11-14 18:18:26 -0700207
208 /* Clear any pending interrupts */
Simon Glassb4ae6002015-01-19 22:16:10 -0700209 rtc_read8(RTC_CONFIG_C);
Simon Glass538059d2014-11-14 18:18:26 -0700210}
Jon Loeliger07efe2a2007-07-10 10:27:39 -0500211#endif