| Masahiro Yamada | 77f0822 | 2015-02-27 02:27:02 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011-2015 Panasonic Corporation |
| 3 | * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <asm/io.h> |
| 10 | #include <mach/sbc-regs.h> |
| 11 | #include <mach/sg-regs.h> |
| 12 | |
| 13 | void sbc_init(void) |
| 14 | { |
| 15 | u32 tmp; |
| 16 | |
| 17 | /* system bus output enable */ |
| 18 | tmp = readl(PC0CTRL); |
| 19 | tmp &= 0xfffffcff; |
| 20 | writel(tmp, PC0CTRL); |
| 21 | |
| 22 | /* XECS1: sub/boot memory (boot swap = off/on) */ |
| 23 | writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); |
| 24 | writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); |
| 25 | writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); |
| 26 | writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); |
| 27 | |
| 28 | /* XECS0: boot/sub memory (boot swap = off/on) */ |
| 29 | writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); |
| 30 | writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); |
| 31 | writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); |
| 32 | writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); |
| 33 | |
| 34 | /* XECS3: peripherals */ |
| 35 | writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); |
| 36 | writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); |
| 37 | writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32); |
| 38 | writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34); |
| 39 | |
| 40 | /* base address regsiters */ |
| 41 | writel(0x0000bc01, SBBASE0); |
| 42 | writel(0x0400bc01, SBBASE1); |
| 43 | writel(0x0800bf01, SBBASE3); |
| 44 | |
| 45 | /* enable access to sub memory when boot swap is on */ |
| 46 | if (boot_is_swapped()) |
| 47 | sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */ |
| 48 | |
| 49 | sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */ |
| 50 | } |