Masahiro Yamada | 1b0a06b | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 1 | # |
| 2 | # USB Host Controller Drivers |
| 3 | # |
| 4 | comment "USB Host Controller Drivers" |
| 5 | |
Masahiro Yamada | 59cfdc0 | 2016-08-01 00:16:34 +0900 | [diff] [blame] | 6 | config USB_HOST |
| 7 | bool |
| 8 | |
Masahiro Yamada | 1b0a06b | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 9 | config USB_XHCI_HCD |
| 10 | bool "xHCI HCD (USB 3.0) support" |
Masahiro Yamada | 59cfdc0 | 2016-08-01 00:16:34 +0900 | [diff] [blame] | 11 | select USB_HOST |
Masahiro Yamada | 1b0a06b | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 12 | ---help--- |
| 13 | The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0 |
| 14 | "SuperSpeed" host controller hardware. |
| 15 | |
Masahiro Yamada | 1b0a06b | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 16 | if USB_XHCI_HCD |
| 17 | |
Masahiro Yamada | d3b72ca | 2016-06-04 07:35:04 +0900 | [diff] [blame] | 18 | config USB_XHCI_DWC3 |
| 19 | bool "DesignWare USB3 DRD Core Support" |
| 20 | help |
| 21 | Say Y or if your system has a Dual Role SuperSpeed |
| 22 | USB controller based on the DesignWare USB3 IP Core. |
| 23 | |
Neil Armstrong | 069421e | 2018-04-11 17:08:00 +0200 | [diff] [blame] | 24 | config USB_XHCI_DWC3_OF_SIMPLE |
| 25 | bool "DesignWare USB3 DRD Generic OF Simple Glue Layer" |
Jean-Jacques Hiblot | 74d9a9d | 2018-04-12 10:41:10 +0200 | [diff] [blame] | 26 | depends on DM_USB |
Mark Kettenis | 06ec913 | 2019-06-30 18:01:54 +0200 | [diff] [blame] | 27 | default y if ARCH_ROCKCHIP |
Jean-Jacques Hiblot | 6c705f4 | 2018-04-12 10:41:11 +0200 | [diff] [blame] | 28 | default y if DRA7XX |
Neil Armstrong | 069421e | 2018-04-11 17:08:00 +0200 | [diff] [blame] | 29 | help |
| 30 | Support USB2/3 functionality in simple SoC integrations with |
| 31 | USB controller based on the DesignWare USB3 IP Core. |
| 32 | |
developer | 507fc9b | 2020-05-02 11:35:18 +0200 | [diff] [blame] | 33 | config USB_XHCI_MTK |
| 34 | bool "Support for MediaTek on-chip xHCI USB controller" |
| 35 | depends on ARCH_MEDIATEK |
| 36 | help |
| 37 | Enables support for the on-chip xHCI controller on MediaTek SoCs. |
| 38 | |
Stefan Roese | 07faf11 | 2016-07-14 11:39:20 +0200 | [diff] [blame] | 39 | config USB_XHCI_MVEBU |
| 40 | bool "MVEBU USB 3.0 support" |
| 41 | default y |
| 42 | depends on ARCH_MVEBU |
Konstantin Porotchkin | 1b5ed4d | 2017-02-12 11:10:30 +0200 | [diff] [blame] | 43 | select DM_REGULATOR |
Stefan Roese | 07faf11 | 2016-07-14 11:39:20 +0200 | [diff] [blame] | 44 | help |
| 45 | Choose this option to add support for USB 3.0 driver on mvebu |
| 46 | SoCs, which includes Armada8K, Armada3700 and other Armada |
| 47 | family SoCs. |
| 48 | |
Stefan Roese | df33b57 | 2020-08-24 13:04:38 +0200 | [diff] [blame] | 49 | config USB_XHCI_OCTEON |
| 50 | bool "Support for Marvell Octeon family on-chip xHCI USB controller" |
| 51 | depends on ARCH_OCTEON |
| 52 | default y |
| 53 | help |
| 54 | Enables support for the on-chip xHCI controller on Marvell Octeon |
| 55 | family SoCs. This is a driver for the dwc3 to provide the glue logic |
| 56 | to configure the controller. |
| 57 | |
Bin Meng | d34d6fc | 2017-07-19 21:50:08 +0800 | [diff] [blame] | 58 | config USB_XHCI_PCI |
| 59 | bool "Support for PCI-based xHCI USB controller" |
Bin Meng | 7e8644d | 2017-07-19 21:51:07 +0800 | [diff] [blame] | 60 | depends on DM_USB |
Bin Meng | d34d6fc | 2017-07-19 21:50:08 +0800 | [diff] [blame] | 61 | default y if X86 |
| 62 | help |
| 63 | Enables support for the PCI-based xHCI controller. |
| 64 | |
Marek Vasut | 2425727 | 2017-10-15 15:01:29 +0200 | [diff] [blame] | 65 | config USB_XHCI_RCAR |
| 66 | bool "Renesas RCar USB 3.0 support" |
| 67 | default y |
| 68 | depends on ARCH_RMOBILE |
| 69 | help |
| 70 | Choose this option to add support for USB 3.0 driver on Renesas |
| 71 | RCar Gen3 SoCs. |
| 72 | |
Patrice Chotard | f2505b1 | 2017-09-05 11:04:24 +0200 | [diff] [blame] | 73 | config USB_XHCI_STI |
| 74 | bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller" |
| 75 | depends on ARCH_STI |
| 76 | default y |
| 77 | help |
| 78 | Enables support for the on-chip xHCI controller on STMicroelectronics |
| 79 | STiH407 family SoCs. This is a driver for the dwc3 to provide the glue logic |
| 80 | to configure the controller. |
| 81 | |
Uri Mashiach | f6ff74e | 2017-02-23 15:39:36 +0200 | [diff] [blame] | 82 | config USB_XHCI_DRA7XX_INDEX |
| 83 | int "DRA7XX xHCI USB index" |
| 84 | range 0 1 |
| 85 | default 0 |
| 86 | depends on DRA7XX |
| 87 | help |
| 88 | Select the DRA7XX xHCI USB index. |
| 89 | Current supported values: 0, 1. |
| 90 | |
Ran Wang | a5a9735 | 2017-10-23 10:09:22 +0800 | [diff] [blame] | 91 | config USB_XHCI_FSL |
| 92 | bool "Support for NXP Layerscape on-chip xHCI USB controller" |
| 93 | default y if ARCH_LS1021A || FSL_LSCH3 || FSL_LSCH2 |
| 94 | depends on !SPL_NO_USB |
| 95 | help |
| 96 | Enables support for the on-chip xHCI controller on NXP Layerscape SoCs. |
Rayagonda Kokatanur | f59d24e | 2020-04-09 09:23:15 +0530 | [diff] [blame] | 97 | |
| 98 | config USB_XHCI_BRCM |
| 99 | bool "Broadcom USB3 Host XHCI controller" |
| 100 | depends on DM_USB |
| 101 | help |
| 102 | USB controller based on the Broadcom USB3 IP Core. |
| 103 | Supports USB2/3 functionality. |
| 104 | |
Masahiro Yamada | 78a9c79 | 2016-08-01 00:16:32 +0900 | [diff] [blame] | 105 | endif # USB_XHCI_HCD |
Alexey Brodkin | 83fd312 | 2015-12-14 17:18:50 +0300 | [diff] [blame] | 106 | |
Masahiro Yamada | 1b0a06b | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 107 | config USB_EHCI_HCD |
| 108 | bool "EHCI HCD (USB 2.0) support" |
Tom Rini | 7716cd6 | 2017-05-12 22:33:28 -0400 | [diff] [blame] | 109 | default y if ARCH_MX5 || ARCH_MX6 |
Masahiro Yamada | 59cfdc0 | 2016-08-01 00:16:34 +0900 | [diff] [blame] | 110 | select USB_HOST |
Masahiro Yamada | 1b0a06b | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 111 | ---help--- |
| 112 | The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0 |
| 113 | "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware. |
| 114 | If your USB host controller supports USB 2.0, you will likely want to |
| 115 | configure this Host Controller Driver. |
| 116 | |
| 117 | EHCI controllers are packaged with "companion" host controllers (OHCI |
| 118 | or UHCI) to handle USB 1.1 devices connected to root hub ports. Ports |
| 119 | will connect to EHCI if the device is high speed, otherwise they |
| 120 | connect to a companion controller. If you configure EHCI, you should |
| 121 | probably configure the OHCI (for NEC and some other vendors) USB Host |
| 122 | Controller Driver or UHCI (for Via motherboards) Host Controller |
| 123 | Driver too. |
| 124 | |
| 125 | You may want to read <file:Documentation/usb/ehci.txt>. |
| 126 | |
Masahiro Yamada | 1b0a06b | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 127 | if USB_EHCI_HCD |
| 128 | |
Wenyou Yang | 11e2665 | 2016-08-05 08:57:35 +0800 | [diff] [blame] | 129 | config USB_EHCI_ATMEL |
| 130 | bool "Support for Atmel on-chip EHCI USB controller" |
| 131 | depends on ARCH_AT91 |
| 132 | default y |
| 133 | ---help--- |
| 134 | Enables support for the on-chip EHCI controller on Atmel chips. |
| 135 | |
Stefan Roese | 0390102 | 2015-09-01 11:39:44 +0200 | [diff] [blame] | 136 | config USB_EHCI_MARVELL |
Tom Rini | 496a417 | 2017-05-12 22:33:29 -0400 | [diff] [blame] | 137 | bool "Support for Marvell on-chip EHCI USB controller" |
Trevor Woerner | bb7ab07 | 2020-05-06 08:02:40 -0400 | [diff] [blame] | 138 | depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X |
Stefan Roese | 0390102 | 2015-09-01 11:39:44 +0200 | [diff] [blame] | 139 | default y |
| 140 | ---help--- |
| 141 | Enables support for the on-chip EHCI controller on MVEBU SoCs. |
| 142 | |
Lukasz Majewski | 6fccaf2 | 2019-04-04 12:26:55 +0200 | [diff] [blame] | 143 | config USB_EHCI_MX5 |
| 144 | bool "Support for i.MX5 on-chip EHCI USB controller" |
| 145 | depends on ARCH_MX5 |
| 146 | default n |
| 147 | help |
| 148 | Enables support for the on-chip EHCI controller on i.MX5 SoCs. |
| 149 | |
Nikita Kiryanov | 9924103 | 2015-07-23 17:19:35 +0300 | [diff] [blame] | 150 | config USB_EHCI_MX6 |
Ye Li | 9da57ea | 2019-10-24 10:29:32 -0300 | [diff] [blame] | 151 | bool "Support for i.MX6/i.MX7ULP on-chip EHCI USB controller" |
Giulio Benetti | 13ded2c | 2021-05-20 16:10:15 +0200 | [diff] [blame] | 152 | depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMXRT |
Nikita Kiryanov | 9924103 | 2015-07-23 17:19:35 +0300 | [diff] [blame] | 153 | default y |
| 154 | ---help--- |
| 155 | Enables support for the on-chip EHCI controller on i.MX6 SoCs. |
| 156 | |
Stefan Agner | 100fe07 | 2016-07-13 00:25:36 -0700 | [diff] [blame] | 157 | config USB_EHCI_MX7 |
| 158 | bool "Support for i.MX7 on-chip EHCI USB controller" |
Marek Vasut | e15971f | 2021-04-02 14:07:22 +0200 | [diff] [blame] | 159 | depends on ARCH_MX7 || IMX8M |
| 160 | select PHY if IMX8M |
| 161 | select NOP_PHY if IMX8M |
Stefan Agner | 100fe07 | 2016-07-13 00:25:36 -0700 | [diff] [blame] | 162 | default y |
| 163 | ---help--- |
| 164 | Enables support for the on-chip EHCI controller on i.MX7 SoCs. |
| 165 | |
Tom Rini | 639a840 | 2017-05-12 22:33:30 -0400 | [diff] [blame] | 166 | config USB_EHCI_OMAP |
| 167 | bool "Support for OMAP3+ on-chip EHCI USB controller" |
| 168 | depends on ARCH_OMAP2PLUS |
| 169 | default y |
| 170 | ---help--- |
| 171 | Enables support for the on-chip EHCI controller on OMAP3 and later |
| 172 | SoCs. |
| 173 | |
Marcel Ziswiler | 31f4495 | 2019-03-25 17:24:54 +0100 | [diff] [blame] | 174 | config USB_EHCI_VF |
| 175 | bool "Support for Vybrid on-chip EHCI USB controller" |
| 176 | depends on ARCH_VF610 |
| 177 | default y |
| 178 | help |
| 179 | Enables support for the on-chip EHCI controller on Vybrid SoCs. |
| 180 | |
Ye Li | 9da57ea | 2019-10-24 10:29:32 -0300 | [diff] [blame] | 181 | if USB_EHCI_MX6 || USB_EHCI_MX7 |
Stefan Agner | 8652ce9 | 2016-07-13 00:25:38 -0700 | [diff] [blame] | 182 | |
| 183 | config MXC_USB_OTG_HACTIVE |
| 184 | bool "USB Power pin high active" |
| 185 | ---help--- |
| 186 | Set the USB Power pin polarity to be high active (PWR_POL) |
| 187 | |
| 188 | endif |
| 189 | |
Mateusz Kulikowski | dc38117 | 2016-03-31 23:12:26 +0200 | [diff] [blame] | 190 | config USB_EHCI_MSM |
| 191 | bool "Support for Qualcomm on-chip EHCI USB controller" |
| 192 | depends on DM_USB |
| 193 | select USB_ULPI_VIEWPORT |
Ramon Fried | 7e36596 | 2018-09-21 13:35:50 +0300 | [diff] [blame] | 194 | select MSM8916_USB_PHY |
Mateusz Kulikowski | dc38117 | 2016-03-31 23:12:26 +0200 | [diff] [blame] | 195 | default n |
| 196 | ---help--- |
| 197 | Enables support for the on-chip EHCI controller on Qualcomm |
| 198 | Snapdragon SoCs. |
Mateusz Kulikowski | dc38117 | 2016-03-31 23:12:26 +0200 | [diff] [blame] | 199 | |
Bin Meng | ec4b573 | 2017-08-09 00:21:54 -0700 | [diff] [blame] | 200 | config USB_EHCI_PCI |
| 201 | bool "Support for PCI-based EHCI USB controller" |
| 202 | default y if X86 |
| 203 | help |
| 204 | Enables support for the PCI-based EHCI controller. |
| 205 | |
Peter Robinson | 43ecef4 | 2019-02-20 12:17:27 +0000 | [diff] [blame] | 206 | config USB_EHCI_TEGRA |
| 207 | bool "Support for NVIDIA Tegra on-chip EHCI USB controller" |
Trevor Woerner | 513f640 | 2020-05-06 08:02:41 -0400 | [diff] [blame] | 208 | depends on ARCH_TEGRA |
Peter Robinson | 43ecef4 | 2019-02-20 12:17:27 +0000 | [diff] [blame] | 209 | ---help--- |
| 210 | Enable support for Tegra on-chip EHCI USB controller |
| 211 | |
Siva Durga Prasad Paladugu | 42fcc18 | 2016-07-22 14:51:51 +0530 | [diff] [blame] | 212 | config USB_EHCI_ZYNQ |
| 213 | bool "Support for Xilinx Zynq on-chip EHCI USB controller" |
Michal Simek | 3239d71 | 2020-08-24 14:41:51 +0200 | [diff] [blame] | 214 | default y if ARCH_ZYNQ |
Siva Durga Prasad Paladugu | 42fcc18 | 2016-07-22 14:51:51 +0530 | [diff] [blame] | 215 | ---help--- |
| 216 | Enable support for Zynq on-chip EHCI USB controller |
| 217 | |
Alexey Brodkin | a6aff43 | 2015-12-02 12:32:02 +0300 | [diff] [blame] | 218 | config USB_EHCI_GENERIC |
| 219 | bool "Support for generic EHCI USB controller" |
| 220 | depends on OF_CONTROL |
| 221 | depends on DM_USB |
Jagan Teki | 1ba41e1 | 2018-12-22 18:18:10 +0530 | [diff] [blame] | 222 | default ARCH_SUNXI |
Alexey Brodkin | a6aff43 | 2015-12-02 12:32:02 +0300 | [diff] [blame] | 223 | default n |
| 224 | ---help--- |
| 225 | Enables support for generic EHCI controller. |
| 226 | |
Ran Wang | 9798b66 | 2017-12-20 10:34:20 +0800 | [diff] [blame] | 227 | config USB_EHCI_FSL |
| 228 | bool "Support for FSL on-chip EHCI USB controller" |
| 229 | default n |
| 230 | select CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 231 | ---help--- |
| 232 | Enables support for the on-chip EHCI controller on FSL chips. |
Masahiro Yamada | 78a9c79 | 2016-08-01 00:16:32 +0900 | [diff] [blame] | 233 | endif # USB_EHCI_HCD |
| 234 | |
| 235 | config USB_OHCI_HCD |
| 236 | bool "OHCI HCD (USB 1.1) support" |
| 237 | ---help--- |
| 238 | The Open Host Controller Interface (OHCI) is a standard for accessing |
| 239 | USB 1.1 host controller hardware. It does more in hardware than Intel's |
| 240 | UHCI specification. If your USB host controller follows the OHCI spec, |
| 241 | say Y. On most non-x86 systems, and on x86 hardware that's not using a |
| 242 | USB controller from Intel or VIA, this is appropriate. If your host |
| 243 | controller doesn't use PCI, this is probably appropriate. For a PCI |
| 244 | based system where you're not sure, the "lspci -v" entry will list the |
| 245 | right "prog-if" for your USB controller(s): EHCI, OHCI, or UHCI. |
| 246 | |
Heiko Schocher | 124f947 | 2019-07-16 10:49:07 +0200 | [diff] [blame] | 247 | config USB_OHCI_PCI |
| 248 | bool "Support for PCI-based OHCI USB controller" |
| 249 | depends on DM_USB |
| 250 | default n |
| 251 | help |
| 252 | Enables support for the PCI-based OHCI controller. |
| 253 | |
Masahiro Yamada | 78a9c79 | 2016-08-01 00:16:32 +0900 | [diff] [blame] | 254 | if USB_OHCI_HCD |
| 255 | |
| 256 | config USB_OHCI_GENERIC |
| 257 | bool "Support for generic OHCI USB controller" |
| 258 | depends on OF_CONTROL |
| 259 | depends on DM_USB |
Jagan Teki | 1ba41e1 | 2018-12-22 18:18:10 +0530 | [diff] [blame] | 260 | default ARCH_SUNXI |
Masahiro Yamada | 59cfdc0 | 2016-08-01 00:16:34 +0900 | [diff] [blame] | 261 | select USB_HOST |
Masahiro Yamada | 78a9c79 | 2016-08-01 00:16:32 +0900 | [diff] [blame] | 262 | ---help--- |
| 263 | Enables support for generic OHCI controller. |
| 264 | |
Adam Ford | 5f364f5 | 2019-04-30 05:21:41 -0500 | [diff] [blame] | 265 | config USB_OHCI_DA8XX |
| 266 | bool "Support for da850 OHCI USB controller" |
| 267 | help |
| 268 | Enable support for the da850 USB controller. |
| 269 | |
Masahiro Yamada | 78a9c79 | 2016-08-01 00:16:32 +0900 | [diff] [blame] | 270 | endif # USB_OHCI_HCD |
Masahiro Yamada | 718ba3c | 2016-08-01 00:16:33 +0900 | [diff] [blame] | 271 | |
| 272 | config USB_UHCI_HCD |
| 273 | bool "UHCI HCD (most Intel and VIA) support" |
Masahiro Yamada | 59cfdc0 | 2016-08-01 00:16:34 +0900 | [diff] [blame] | 274 | select USB_HOST |
Masahiro Yamada | 718ba3c | 2016-08-01 00:16:33 +0900 | [diff] [blame] | 275 | ---help--- |
| 276 | The Universal Host Controller Interface is a standard by Intel for |
| 277 | accessing the USB hardware in the PC (which is also called the USB |
| 278 | host controller). If your USB host controller conforms to this |
| 279 | standard, you may want to say Y, but see below. All recent boards |
| 280 | with Intel PCI chipsets (like intel 430TX, 440FX, 440LX, 440BX, |
| 281 | i810, i820) conform to this standard. Also all VIA PCI chipsets |
| 282 | (like VIA VP2, VP3, MVP3, Apollo Pro, Apollo Pro II or Apollo Pro |
| 283 | 133) and LEON/GRLIB SoCs with the GRUSBHC controller. |
| 284 | If unsure, say Y. |
| 285 | |
| 286 | if USB_UHCI_HCD |
| 287 | |
| 288 | endif # USB_UHCI_HCD |
Philipp Tomsich | 5498381 | 2017-07-03 18:30:06 +0200 | [diff] [blame] | 289 | |
| 290 | config USB_DWC2 |
| 291 | bool "DesignWare USB2 Core support" |
| 292 | select USB_HOST |
| 293 | ---help--- |
| 294 | The DesignWare USB 2.0 controller is compliant with the |
| 295 | USB-Implementers Forum (USB-IF) USB 2.0 specifications. |
| 296 | Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps) |
| 297 | operation is compliant to the controller Supplement. If you want to |
| 298 | enable this controller in host mode, say Y. |
Alexey Brodkin | f19414b | 2018-02-28 16:16:58 +0300 | [diff] [blame] | 299 | |
| 300 | if USB_DWC2 |
| 301 | config USB_DWC2_BUFFER_SIZE |
| 302 | int "Data buffer size in kB" |
| 303 | default 64 |
| 304 | ---help--- |
| 305 | By default 64 kB buffer is used but if amount of RAM avaialble on |
| 306 | the target is not enough to accommodate allocation of buffer of |
| 307 | that size it is possible to shrink it. Smaller sizes should be fine |
| 308 | because larger transactions could be split in smaller ones. |
| 309 | |
| 310 | endif # USB_DWC2 |
Marek Vasut | 8801603 | 2019-08-11 13:23:43 +0200 | [diff] [blame] | 311 | |
| 312 | config USB_R8A66597_HCD |
| 313 | bool "Renesas R8A66597 USB Core support" |
| 314 | depends on OF_CONTROL |
| 315 | depends on DM_USB |
| 316 | select USB_HOST |
| 317 | ---help--- |
| 318 | This enables support for the on-chip Renesas R8A66597 USB 2.0 |
| 319 | controller, present in various RZ and SH SoCs. |