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git01.mediatek.com / filogic / uboot / 5b96863b3f3ebe46650f26b6a32aa70e57765540 / . / include / configs / adp-ag102.h
blob: c46eed9eada031fc8383a58164125fbbd6e49731 [file] [log] [blame]
Macpaul Lin80a9b132011-09-23 16:49:59 +0800[diff] [blame]1/*
2 * Copyright (C) 2011 Andes Technology Corporation
3 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Macpaul Lin80a9b132011-09-23 16:49:59 +0800[diff] [blame]6 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#include <asm/arch/ag102.h>
12
13/*
14 * CPU and Board Configuration Options
15 */
16#define CONFIG_ADP_AG102
17
18#define CONFIG_USE_INTERRUPT
19
20#define CONFIG_SKIP_LOWLEVEL_INIT
21
22#ifndef CONFIG_SKIP_LOWLEVEL_INIT
23#define CONFIG_MEM_REMAP
24#endif
25
26#ifdef CONFIG_SKIP_LOWLEVEL_INIT
27#define CONFIG_SYS_TEXT_BASE 0x04200000
28#else
29#define CONFIG_SYS_TEXT_BASE 0x00000000
30#endif
31
32/*
33 * Timer
34 */
Macpaul Lin80a9b132011-09-23 16:49:59 +0800[diff] [blame]35#define CONFIG_SYS_CLK_FREQ (66000000 * 2)
36#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
37
38/*
39 * Use Externel CLOCK or PCLK
40 */
41#undef CONFIG_FTRTC010_EXTCLK
42
43#ifndef CONFIG_FTRTC010_EXTCLK
44#define CONFIG_FTRTC010_PCLK
45#endif
46
47#ifdef CONFIG_FTRTC010_EXTCLK
48#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
49#else
50#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
51#endif
52
53#define TIMER_LOAD_VAL 0xffffffff
54
55/*
56 * Real Time Clock
57 */
58#define CONFIG_RTC_FTRTC010
59
60/*
61 * Real Time Clock Divider
62 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
63 */
64#define OSC_5MHZ (5*1000000)
65#define OSC_CLK (2*OSC_5MHZ)
66#define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
67
68/*
69 * Serial console configuration
70 */
71
72/* FTUART is a high speed NS 16C550A compatible UART */
73#define CONFIG_BAUDRATE 38400
74#define CONFIG_CONS_INDEX 1
75#define CONFIG_SYS_NS16550
76#define CONFIG_SYS_NS16550_SERIAL
77#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_01_BASE
78#define CONFIG_SYS_NS16550_REG_SIZE -4
79#define CONFIG_SYS_NS16550_CLK 33000000 /* AG102 */
80
Macpaul Lin80a9b132011-09-23 16:49:59 +0800[diff] [blame]81/*
82 * Ethernet
83 */
Macpaul Lin80a9b132011-09-23 16:49:59 +0800[diff] [blame]84#define CONFIG_PHY_MAX_ADDR 32 /* this comes from <linux/phy.h> */
85#define CONFIG_SYS_DISCOVER_PHY
86#define CONFIG_FTGMAC100
87#define CONFIG_FTGMAC100_EGIGA
88
89#define CONFIG_BOOTDELAY 3
90
91/*
92 * SD (MMC) controller
93 */
94#define CONFIG_MMC
95#define CONFIG_CMD_MMC
96#define CONFIG_GENERIC_MMC
97#define CONFIG_DOS_PARTITION
98#define CONFIG_FTSDC010
99#define CONFIG_FTSDC010_NUMBER 1
100#define CONFIG_FTSDC010_SDIO
101#define CONFIG_CMD_FAT
102#define CONFIG_CMD_EXT2
103
104/*
105 * Command line configuration.
106 */
107#include <config_cmd_default.h>
108
109#define CONFIG_CMD_CACHE
110#define CONFIG_CMD_DATE
111#define CONFIG_CMD_PING
112#define CONFIG_CMD_IDE
113#define CONFIG_CMD_FAT
114#define CONFIG_CMD_ELF
115
116#undef CONFIG_CMD_FLASH
117#undef CONFIG_CMD_IMLS
118
119/*
120 * PCI
121 */
122#define CONFIG_PCI
123#define CONFIG_FTPCI100
Gabor Juhosb4458732013-05-30 07:06:12 +0000[diff] [blame]124#define CONFIG_PCI_INDIRECT_BRIDGE
Macpaul Lin80a9b132011-09-23 16:49:59 +0800[diff] [blame]125#define CONFIG_FTPCI100_MEM_BASE 0xa0000000
126#define CONFIG_FTPCI100_IO_SIZE FTPCI100_BASE_IO_SIZE(256) /* 256M */
127#define CONFIG_FTPCI100_MEM_SIZE FTPCI100_MEM_SIZE(128) /* 128M */
128#define CONFIG_FTPCI100_MEM_BASE_SIZE1 0x50
129
130#define CONFIG_PCI_MEM_BUS 0xa0000000
131#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
132#define CONFIG_PCI_MEM_SIZE 0x01000000 /* 256M */
133
134#define CONFIG_PCI_IO_BUS 0x90000000
135#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
136#define CONFIG_PCI_IO_SIZE 0x00100000 /* 1M */
137
138/*
139 * USB
140 */
141#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
142#if defined(CONFIG_FTPCI100)
143#define __io /* enable outl & inl */
144#define CONFIG_CMD_USB
145#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 5
146#define CONFIG_USB_STORAGE
147#define CONFIG_USB_EHCI
148#define CONFIG_PCI_EHCI_DEVICE 0
149#define CONFIG_USB_EHCI_PCI
150#define CONFIG_PREBOOT "usb start;"
151#endif /* #if defiend(CONFIG_FTPCI100) */
152#endif /* #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) */
153
154/*
155 * IDE/ATA stuff
156 */
157#define __io
158#define CONFIG_IDE_AHB
159#define CONFIG_IDE_FTIDE020
160
161#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
162#undef CONFIG_IDE_LED /* no led for ide supported */
163#define CONFIG_IDE_RESET 1 /* reset for ide supported */
164#define CONFIG_IDE_PREINIT 1 /* preinit for ide */
165
166/* max: 2 IDE busses */
167#define CONFIG_SYS_IDE_MAXBUS 1 /* origin: 2 */
168/* max: 2 drives per IDE bus */
169#define CONFIG_SYS_IDE_MAXDEVICE 1 /* origin: (MAXBUS * 2) */
170
171#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_FTIDE020S_BASE
172#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
173#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0000
174
175#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* for data I/O */
176#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* for normal regs access */
177#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* for alternate regs */
178
179#define CONFIG_MAC_PARTITION
180#define CONFIG_DOS_PARTITION
181#define CONFIG_SUPPORT_VFAT
182
183/*
184 * Miscellaneous configurable options
185 */
186#define CONFIG_SYS_LONGHELP /* undef to save memory */
187#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */
188#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
189
190/* Print Buffer Size */
191#define CONFIG_SYS_PBSIZE \
192 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
193
194/* max number of command args */
195#define CONFIG_SYS_MAXARGS 16
196
197/* Boot Argument Buffer Size */
198#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
199
200/*
Macpaul Lin80a9b132011-09-23 16:49:59 +0800[diff] [blame]201 * Size of malloc() pool
202 */
203#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
204
205/*
Macpaul Lin80a9b132011-09-23 16:49:59 +0800[diff] [blame]206 * AHB Controller configuration
207 */
208#define CONFIG_FTAHBC020S
209
210#ifdef CONFIG_FTAHBC020S
211#include <faraday/ftahbc020s.h>
212
213/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
214#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
215
216/*
217 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
218 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
219 * in C language.
220 */
221#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
222 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
223 FTAHBC020S_SLAVE_BSR_SIZE(0xb))
224#endif
225
226/*
227 * Watchdog
228 */
229#define CONFIG_FTWDT010_WATCHDOG
230
231/*
232 * PCU Power Control Unit configuration
233 */
234#define CONFIG_ANDES_PCU
235
236#ifdef CONFIG_ANDES_PCU
237#include <andestech/andes_pcu.h>
238
239#endif
240
241/*
242 * DDR DRAM controller configuration
243 */
244#define CONFIG_DWCDDR21MCTL
245
246#ifdef CONFIG_DWCDDR21MCTL
247#include <synopsys/dwcddr21mctl.h>
248/* DCR:
249 * 2GB: 0x000025d2, 2GB (1Gb x8 2 ranks) Micron/innoDisk/Transcend
250 * 1GB: 0x000021d2, 1GB (1Gb x8 1 rank) Micron/Transcend/innoDisk
251 * 512MB: 0x000025cc, Micron 512MB (512Mb x16 2 ranks)
252 * 512MB: 0x000021ca, Trenscend/innoDisk 512MB (512Mb x8 1 rank)
253 * 256MB: 0x000020d4, Micron 256MB (1Gb x16 1 ranks)
254 */
255#define CONFIG_SYS_DWCDDR21MCTL_CCR 0x00020004
256#define CONFIG_SYS_DWCDDR21MCTL_CCR2 (DWCDDR21MCTL_CCR_DTT(0x1) | \
257 DWCDDR21MCTL_CCR_DFTLM(0x4) | \
258 DWCDDR21MCTL_CCR_HOSTEN(0x1))
259
260/* 0x04: 0x000020d4 */
261#define CONFIG_SYS_DWCDDR21MCTL_DCR 0x000020ca
262
263/* 0x08: 0x0000000f */
264#define CONFIG_SYS_DWCDDR21MCTL_IOCR 0x0000000f
265
266/* 0x10: 0x00034812 */
267#define CONFIG_SYS_DWCDDR21MCTL_DRR (DWCDDR21MCTL_DRR_TRFC(0x12) | \
268 DWCDDR21MCTL_DRR_TRFPRD(0x0348))
269/* 0x24 */
270#define CONFIG_SYS_DWCDDR21MCTL_DLLCR0 DWCDDR21MCTL_DLLCR_PHASE(0x0)
271
272/* 0x4c: 0x00000040 */
273#define CONFIG_SYS_DWCDDR21MCTL_RSLR0 0x00000040
274
275/* 0x5c: 0x000055CF */
276#define CONFIG_SYS_DWCDDR21MCTL_RDGR0 0x000055cf
277
278/* 0xa4: 0x00100000 */
279#define CONFIG_SYS_DWCDDR21MCTL_DTAR (DWCDDR21MCTL_DTAR_DTBANK(0x0) | \
280 DWCDDR21MCTL_DTAR_DTROW(0x0100) | \
281 DWCDDR21MCTL_DTAR_DTCOL(0x0))
282/* 0x1f0: 0x00000852 */
283#define CONFIG_SYS_DWCDDR21MCTL_MR (DWCDDR21MCTL_MR_WR(0x4) | \
284 DWCDDR21MCTL_MR_CL(0x5) | \
285 DWCDDR21MCTL_MR_BL(0x2))
286#endif
287
288/*
289 * Physical Memory Map
290 */
291#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
292#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
293#if defined(CONFIG_MEM_REMAP)
294#define PHYS_SDRAM_0_AT_INIT 0x80000000 /* SDRAM Bank #1 before remap*/
295#endif
296#else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
297#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
298#endif
299
300#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
301#define PHYS_SDRAM_0_SIZE 0x10000000 /* 256 MB */
302
303#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
304
305#ifdef CONFIG_MEM_REMAP
306#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
307 GENERATED_GBL_DATA_SIZE)
308#else
309#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
310 GENERATED_GBL_DATA_SIZE)
311#endif /* CONFIG_MEM_REMAP */
312
313/*
314 * Load address and memory test area should agree with
315 * board/faraday/a320/config.mk
316 * Be careful not to overwrite U-boot itself.
317 */
318#define CONFIG_SYS_LOAD_ADDR 0x0CF00000
319
320/* memtest works on 63 MB in DRAM */
321#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
322#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
323
324/*
325 * Static memory controller configuration
326 */
327
328/*
329 * FLASH and environment organization
330 */
331#define CONFIG_SYS_NO_FLASH
332
333/*
334 * Env Storage Settings
335 */
336#define CONFIG_ENV_IS_NOWHERE
337#define CONFIG_ENV_SIZE 4096
338
339#endif /* __CONFIG_H */