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wdenk327f7a02001-11-28 17:49:55 +00001#ifndef DMA_H
2#define DMA_H
3/*******************************************************
4 *
5 * copyright @ Motorola 1999
6 *
7 *******************************************************/
8#define NUM_DMA_REG 7
9#define DMA_MR_REG 0
10#define DMA_SR_REG 1
11#define DMA_CDAR_REG 2
12#define DMA_SAR_REG 3
13#define DMA_DAR_REG 4
14#define DMA_BCR_REG 5
15#define DMA_NDAR_REG 6
16
17typedef enum _dmastatus
18{
19 DMASUCCESS = 0x1000,
20 DMALMERROR,
21 DMAPERROR,
22 DMACHNBUSY,
23 DMAEOSINT,
24 DMAEOCAINT,
25 DMAINVALID,
26 DMANOEVENT,
27} DMAStatus;
28
29typedef enum _location
30{
31 LOCAL = 0, /* local processor accesses on board DMA,
32 local processor's eumbbar is required */
33 REMOTE = 1, /* PCI master accesses DMA on I/O board,
34 I/O processor's pcsrbar is required */
35} LOCATION;
36
37typedef enum dma_mr_bit
38{
39 IRQS = 0x00080000,
40 PDE = 0x00040000,
41 DAHTS = 0x00030000,
42 SAHTS = 0x0000c000,
43 DAHE = 0x00002000,
44 SAHE = 0x00001000,
45 PRC = 0x00000c00,
46 EIE = 0x00000080,
47 EOTIE = 0x00000040,
48 DL = 0x00000008,
49 CTM = 0x00000004,
50 CC = 0x00000002,
51 CS = 0x00000001,
52} DMA_MR_BIT;
53
54typedef enum dma_sr_bit
55{
56 LME = 0x00000080,
57 PE = 0x00000010,
58 CB = 0x00000004,
59 EOSI = 0x00000002,
60 EOCAI = 0x00000001,
61} DMA_SR_BIT;
62
63/* structure for DMA Mode Register */
64typedef struct _dma_mr
65{
66 unsigned int reserved0 : 12;
67 unsigned int irqs : 1;
68 unsigned int pde : 1;
69 unsigned int dahts : 2;
70 unsigned int sahts : 2;
71 unsigned int dahe : 1;
72 unsigned int sahe : 1;
73 unsigned int prc : 2;
74 unsigned int reserved1 : 1;
75 unsigned int eie : 1;
76 unsigned int eotie : 1;
77 unsigned int reserved2 : 3;
78 unsigned int dl : 1;
79 unsigned int ctm : 1;
80 /* if chaining mode is enabled, any time, user can modify the
81 * descriptor and does not need to halt the current DMA transaction.
82 * Set CC bit, enable DMA to process the modified descriptors
83 * Hardware will clear this bit each time, DMA starts.
84 */
85 unsigned int cc : 1;
86 /* cs bit has dua role, halt the current DMA transaction and
87 * (re)start DMA transaction. In chaining mode, if the descriptor
88 * needs modification, cs bit shall be used not the cc bit.
89 * Hardware will not set/clear this bit each time DMA transaction
90 * stops or starts. Software shall do it.
91 *
92 * cs bit shall not be used to halt chaining DMA transaction for
93 * modifying the descriptor. That is the role of CC bit.
94 */
95 unsigned int cs : 1;
96} DMA_MR;
97
98/* structure for DMA Status register */
99typedef struct _dma_sr
100{
101 unsigned int reserved0 : 24;
102 unsigned int lme : 1;
103 unsigned int reserved1 : 2;
104 unsigned int pe : 1;
105 unsigned int reserved2 : 1;
106 unsigned int cb : 1;
107 unsigned int eosi : 1;
108 unsigned int eocai : 1;
109} DMA_SR;
110
111/* structure for DMA current descriptor address register */
112typedef struct _dma_cdar
113{
114 unsigned int cda : 27;
115 unsigned int snen : 1;
116 unsigned int eosie : 1;
117 unsigned int ctt : 2;
118 unsigned int eotd : 1;
119} DMA_CDAR;
120
121/* structure for DMA byte count register */
122typedef struct _dma_bcr
123{
124 unsigned int reserved : 6;
125 unsigned int bcr : 26;
126} DMA_BCR;
127
128/* structure for DMA Next Descriptor Address register */
129typedef struct _dma_ndar
130{
131 unsigned int nda : 27;
132 unsigned int ndsnen : 1;
133 unsigned int ndeosie: 1;
134 unsigned int ndctt : 2;
135 unsigned int eotd : 1;
136} DMA_NDAR;
137
138/* structure for DMA current transaction info */
139typedef struct _dma_curr
140{
141 unsigned int src_addr;
142 unsigned int dest_addr;
143 unsigned int byte_cnt;
144} DMA_CURR;
145
146/************************* Kernel API********************
147 * Kernel APIs are used to interface with O.S. kernel.
148 * They are the functions required by O.S. kernel to
149 * provide I/O service.
150 ********************************************************/
151
152/**************DMA Device Control Functions ********/
153
154/**
155 * Note:
156 *
157 * In all following functions, the host (KAHLUA) processor has a
158 * choice of accessing on board local DMA (LOCAL),
159 * or DMA on a distributed KAHLUA (REMOTE). In either case,
160 * the caller shall pass the configured embedded utility memory
161 * block base address relative to the DMA. If LOCAL DMA is used,
162 * this parameter shall be EUMBBAR, if REMOTE is used, the
163 * parameter shall be the corresponding PCSRBAR.
164 **/
165
166/**************************************************************
167 * function: DMA_Get_Stat
168 *
169 * description: return the content of status register of
170 * the given DMA channel
171 * if error, return DMAINVALID. Otherwise return
172 * DMASUCCESS.
173 *
174 **************************************************************/
175static DMAStatus DMA_Get_Stat( LOCATION, unsigned int eumbbar, unsigned int channel, DMA_SR * );
176
177/**************************************************************
178 * function: DMA_Get_Mode
179 *
180 * description: return the content of mode register of the
181 * given DMA channel
182 * if error, return DMAINVALID. Otherwise return DMASUCCESS.
183 *
184 **************************************************************/
185static DMAStatus DMA_Get_Mode( LOCATION, unsigned int eumbbar, unsigned int channel, DMA_MR * );
186
187/**************************************************************
188 * function: DMA_Set_Mode
189 *
190 * description: Set a new mode to a given DMA channel
191 * return DMASUCCESS if success, otherwise return DMACHNINVALID
192 *
193 * note: It is not a good idea of changing the DMA mode during
194 * the middle of a transaction.
195 **************************************************************/
196static DMAStatus DMA_Set_Mode( LOCATION, unsigned int eumbbar, unsigned int channel, DMA_MR mode );
197
198/*************************************************************
199 * function: DMA_ISR
200 *
201 * description: DMA interrupt service routine
202 * return DMAStatus based on the status
203 *
204 *************************************************************/
205static DMAStatus DMA_ISR( unsigned int eumbbar,
206 unsigned int channel,
207 DMAStatus (*lme_func)( unsigned int, unsigned int, DMAStatus ),
208 DMAStatus (*pe_func) ( unsigned int, unsigned int, DMAStatus ),
209 DMAStatus (*eosi_func)( unsigned int, unsigned int, DMAStatus ),
210 DMAStatus (*eocai_func)(unsigned int, unsigned int, DMAStatus ));
211
212static DMAStatus dma_error_func( unsigned int, unsigned int, DMAStatus );
213
214/********************* DMA I/O function ********************/
215
216/************************************************************
217 * function: DMA_Start
218 *
219 * description: start a given DMA channel transaction
220 * return DMASUCCESS if success, otherwise return DMACHNINVALID
221 *
222 * note: this function will clear DMA_MR(CC) first, then
223 * set DMA_MR(CC).
224 ***********************************************************/
225static DMAStatus DMA_Start( LOCATION, unsigned int eumbbar,unsigned int channel );
226
227/***********************************************************
228 * function: DMA_Halt
229 *
230 * description: halt the current dma transaction on the specified
231 * channel.
232 * return DMASUCCESS if success, otherwise return DMACHNINVALID
233 *
234 * note: if the specified DMA channel is idle, nothing happens
235 *************************************************************/
236static DMAStatus DMA_Halt( LOCATION, unsigned int eumbbar,unsigned int channel );
237
238/*************************************************************
239 * function: DMA_Chn_Cnt
240 *
241 * description: set the DMA_MR(CC) bit for a given channel
242 * that is in chaining mode.
243 * return DMASUCCESS if successfule, otherwise return DMACHNINVALID
244 *
245 * note: if the given channel is not in chaining mode, nothing
246 * happen.
247 *
248 *************************************************************/
249static DMAStatus DMA_Chn_Cnt( LOCATION, unsigned int eumbbar,unsigned int channel );
250
251/*********************** App. API ***************************
252 * App. API are the APIs Kernel provides for the application
253 * level program
254 ************************************************************/
255/**************************************************************
256 * function: DMA_Bld_Curr
257 *
258 * description: set current src, dest, byte count registers
259 * according to the desp for a given channel
260 *
261 * if the given channel is busy, no change made,
262 * return DMACHNBUSY.
263 *
264 * otherwise return DMASUCCESS.
265 *
266 * note:
267 **************************************************************/
268static DMAStatus DMA_Bld_Curr( LOCATION,
269 unsigned int eumbbar,
270 unsigned int channel,
271 DMA_CURR desp );
272
273/**************************************************************
274 * function: DMA_Poke_Curr
275 *
276 * description: poke the current src, dest, byte count registers
277 * for a given channel.
278 *
279 * return DMASUCCESS if no error otherwise return DMACHNERROR
280 *
281 * note: Due to the undeterministic parallelism, in chaining
282 * mode, the value returned by this function shall
283 * be taken as reference when the query is made rather
284 * than the absolute snapshot when the value is returned.
285 **************************************************************/
286static DMAStatus DMA_Poke_Curr( LOCATION,
287 unsigned int eumbbar,
288 unsigned int channel,
289 DMA_CURR* desp );
290
291/**************************************************************
292 * function: DMA_Bld_Desp
293 *
294 * description: set current descriptor address register
295 * according to the desp for a given channel
296 *
297 * if the given channel is busy return DMACHNBUSY
298 * and no change made, otherwise return DMASUCCESS.
299 *
300 * note:
301 **************************************************************/
302static DMAStatus DMA_Bld_Desp( LOCATION host,
303 unsigned int eumbbar,
304 unsigned int channel,
305 DMA_CDAR desp );
306
307/**************************************************************
308 * function: DMA_Poke_Desp
309 *
310 * description: poke the current descriptor address register
311 * for a given channel
312 *
313 * return DMASUCCESS if no error otherwise return
314 * DMAINVALID
315 *
316 * note: Due to the undeterministic parallellism of DMA operation,
317 * the value returned by this function shall be taken as
318 * the most recently used descriptor when the last time
319 * DMA starts a chaining mode operation.
320 **************************************************************/
321static DMAStatus DMA_Poke_Desp( LOCATION,
322 unsigned int eumbbar,
323 unsigned int channel,
324 DMA_CDAR *desp );
325
326#endif