blob: 7d81036647e28d9b992cf2c59b72ac66072ef9c0 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkc4cbd342005-01-09 18:21:42 +00002/*
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenkc4cbd342005-01-09 18:21:42 +00005 */
6
Tom Rinidec7ea02024-05-20 13:35:03 -06007#include <config.h>
Simon Glassa73bda42015-11-08 23:47:45 -07008#include <console.h>
Simon Glass1d91ba72019-11-14 12:57:37 -07009#include <cpu_func.h>
Simon Glass8e201882020-05-10 11:39:54 -060010#include <flash.h>
Simon Glass8f3f7612019-11-14 12:57:42 -070011#include <irq_func.h>
Tom Rinidec7ea02024-05-20 13:35:03 -060012#include <stdio.h>
13#include <time.h>
Caleb Connolly29cab7c2024-08-30 13:34:37 +010014#include <u-boot/uuid.h>
Tom Rinidec7ea02024-05-20 13:35:03 -060015#include <vsprintf.h>
Simon Glassdbd79542020-05-10 11:40:11 -060016#include <linux/delay.h>
Tom Rinidec7ea02024-05-20 13:35:03 -060017#include <linux/string.h>
wdenkc4cbd342005-01-09 18:21:42 +000018
Tom Rini6a5dccc2022-11-16 13:10:41 -050019#define PHYS_FLASH_1 CFG_SYS_FLASH_BASE
wdenkc4cbd342005-01-09 18:21:42 +000020#define FLASH_BANK_SIZE 0x200000
21
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020022flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
wdenkc4cbd342005-01-09 18:21:42 +000023
Simon Glassc7443162020-05-10 11:39:53 -060024void flash_print_info(flash_info_t *info)
wdenkc4cbd342005-01-09 18:21:42 +000025{
26 int i;
27
28 switch (info->flash_id & FLASH_VENDMASK) {
29 case (AMD_MANUFACT & FLASH_VENDMASK):
30 printf ("AMD: ");
31 break;
32 default:
33 printf ("Unknown Vendor ");
34 break;
35 }
36
37 switch (info->flash_id & FLASH_TYPEMASK) {
38 case (AMD_ID_PL160CB & FLASH_TYPEMASK):
39 printf ("AM29PL160CB (16Mbit)\n");
40 break;
41 default:
42 printf ("Unknown Chip Type\n");
43 goto Done;
44 break;
45 }
46
47 printf (" Size: %ld MB in %d Sectors\n",
48 info->size >> 20, info->sector_count);
49
50 printf (" Sector Start Addresses:");
51 for (i = 0; i < info->sector_count; i++) {
52 if ((i % 5) == 0) {
53 printf ("\n ");
54 }
55 printf (" %08lX%s", info->start[i],
56 info->protect[i] ? " (RO)" : " ");
57 }
58 printf ("\n");
59
60Done:
Marian Balakowicz3e8b1dc2006-05-09 11:28:36 +020061 return;
wdenkc4cbd342005-01-09 18:21:42 +000062}
63
Simon Glassc7443162020-05-10 11:39:53 -060064unsigned long flash_init(void)
wdenkc4cbd342005-01-09 18:21:42 +000065{
66 int i, j;
67 ulong size = 0;
68
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020069 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
wdenkc4cbd342005-01-09 18:21:42 +000070 ulong flashbase = 0;
71
72 flash_info[i].flash_id =
73 (AMD_MANUFACT & FLASH_VENDMASK) |
74 (AMD_ID_PL160CB & FLASH_TYPEMASK);
75 flash_info[i].size = FLASH_BANK_SIZE;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020076 flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
77 memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
wdenkc4cbd342005-01-09 18:21:42 +000078 if (i == 0)
79 flashbase = PHYS_FLASH_1;
80 else
81 panic ("configured to many flash banks!\n");
82
83 for (j = 0; j < flash_info[i].sector_count; j++) {
84 if (j == 0) {
85 /* 1st is 16 KiB */
86 flash_info[i].start[j] = flashbase;
87 }
88 if ((j >= 1) && (j <= 2)) {
89 /* 2nd and 3rd are 8 KiB */
90 flash_info[i].start[j] =
91 flashbase + 0x4000 + 0x2000 * (j - 1);
92 }
93 if (j == 3) {
94 /* 4th is 224 KiB */
95 flash_info[i].start[j] = flashbase + 0x8000;
96 }
97 if ((j >= 4) && (j <= 10)) {
98 /* rest is 256 KiB */
99 flash_info[i].start[j] =
100 flashbase + 0x40000 + 0x40000 * (j -
101 4);
102 }
103 }
104 size += flash_info[i].size;
105 }
106
Simon Glassc7443162020-05-10 11:39:53 -0600107 flash_protect(FLAG_PROTECT_SET,
Tom Rini6a5dccc2022-11-16 13:10:41 -0500108 CFG_SYS_FLASH_BASE,
109 CFG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]);
wdenkc4cbd342005-01-09 18:21:42 +0000110
111 return size;
112}
113
wdenkc4cbd342005-01-09 18:21:42 +0000114#define CMD_READ_ARRAY 0x00F0
115#define CMD_UNLOCK1 0x00AA
116#define CMD_UNLOCK2 0x0055
117#define CMD_ERASE_SETUP 0x0080
118#define CMD_ERASE_CONFIRM 0x0030
119#define CMD_PROGRAM 0x00A0
120#define CMD_UNLOCK_BYPASS 0x0020
121
Tom Rini6a5dccc2022-11-16 13:10:41 -0500122#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_SYS_FLASH_BASE + (0x00000555<<1)))
123#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_SYS_FLASH_BASE + (0x000002AA<<1)))
wdenkc4cbd342005-01-09 18:21:42 +0000124
125#define BIT_ERASE_DONE 0x0080
126#define BIT_RDY_MASK 0x0080
127#define BIT_PROGRAM_ERROR 0x0020
128#define BIT_TIMEOUT 0x80000000 /* our flag */
129
130#define READY 1
131#define ERR 2
132#define TMO 4
133
Simon Glassc7443162020-05-10 11:39:53 -0600134int flash_erase(flash_info_t *info, int s_first, int s_last)
wdenkc4cbd342005-01-09 18:21:42 +0000135{
136 ulong result;
137 int iflag, cflag, prot, sect;
Jerome Forissier523bc4d2024-09-11 11:58:15 +0200138 int rc = FL_ERR_OK;
wdenkc4cbd342005-01-09 18:21:42 +0000139 int chip1;
Graeme Russ43f02552011-06-28 01:40:55 +0000140 ulong start;
wdenkc4cbd342005-01-09 18:21:42 +0000141
142 /* first look for protection bits */
143
144 if (info->flash_id == FLASH_UNKNOWN)
Jerome Forissier523bc4d2024-09-11 11:58:15 +0200145 return FL_ERR_UNKNOWN_FLASH_TYPE;
wdenkc4cbd342005-01-09 18:21:42 +0000146
147 if ((s_first < 0) || (s_first > s_last)) {
Jerome Forissier523bc4d2024-09-11 11:58:15 +0200148 return FL_ERR_INVAL;
wdenkc4cbd342005-01-09 18:21:42 +0000149 }
150
151 if ((info->flash_id & FLASH_VENDMASK) !=
152 (AMD_MANUFACT & FLASH_VENDMASK)) {
Jerome Forissier523bc4d2024-09-11 11:58:15 +0200153 return FL_ERR_UNKNOWN_FLASH_VENDOR;
wdenkc4cbd342005-01-09 18:21:42 +0000154 }
155
156 prot = 0;
157 for (sect = s_first; sect <= s_last; ++sect) {
158 if (info->protect[sect]) {
159 prot++;
160 }
161 }
162 if (prot)
Jerome Forissier523bc4d2024-09-11 11:58:15 +0200163 return FL_ERR_PROTECTED;
wdenkc4cbd342005-01-09 18:21:42 +0000164
165 /*
166 * Disable interrupts which might cause a timeout
167 * here. Remember that our exception vectors are
168 * at address 0 in the flash, and we don't want a
169 * (ticker) exception to happen while the flash
170 * chip is in programming mode.
171 */
172
Simon Glassfbf091b2019-11-14 12:57:36 -0700173 cflag = icache_status();
174 icache_disable();
Simon Glassf87959b2019-11-14 12:57:40 -0700175 iflag = disable_interrupts();
wdenkc4cbd342005-01-09 18:21:42 +0000176
177 printf ("\n");
178
179 /* Start erase on unprotected sectors */
180 for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
181 printf ("Erasing sector %2d ... ", sect);
182
183 /* arm simple, non interrupt dependent timer */
Graeme Russ43f02552011-06-28 01:40:55 +0000184 start = get_timer(0);
wdenkc4cbd342005-01-09 18:21:42 +0000185
186 if (info->protect[sect] == 0) { /* not protected */
187 volatile u16 *addr =
188 (volatile u16 *) (info->start[sect]);
189
190 MEM_FLASH_ADDR1 = CMD_UNLOCK1;
191 MEM_FLASH_ADDR2 = CMD_UNLOCK2;
192 MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
193
194 MEM_FLASH_ADDR1 = CMD_UNLOCK1;
195 MEM_FLASH_ADDR2 = CMD_UNLOCK2;
196 *addr = CMD_ERASE_CONFIRM;
197
198 /* wait until flash is ready */
199 chip1 = 0;
200
201 do {
202 result = *addr;
203
Tom Rini78f88002022-07-23 13:05:00 -0400204 /* check timeout, 1000ms */
205 if (get_timer(start) > 1000) {
wdenkc4cbd342005-01-09 18:21:42 +0000206 MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
207 chip1 = TMO;
208 break;
209 }
210
211 if (!chip1
212 && (result & 0xFFFF) & BIT_ERASE_DONE)
213 chip1 = READY;
214
215 } while (!chip1);
216
217 MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
218
219 if (chip1 == ERR) {
Jerome Forissier523bc4d2024-09-11 11:58:15 +0200220 rc = FL_ERR_PROG_ERROR;
wdenkc4cbd342005-01-09 18:21:42 +0000221 goto outahere;
222 }
223 if (chip1 == TMO) {
Jerome Forissier523bc4d2024-09-11 11:58:15 +0200224 rc = FL_ERR_TIMEOUT;
wdenkc4cbd342005-01-09 18:21:42 +0000225 goto outahere;
226 }
227
228 printf ("ok.\n");
229 } else { /* it was protected */
230
231 printf ("protected!\n");
232 }
233 }
234
235 if (ctrlc ())
236 printf ("User Interrupt!\n");
237
238 outahere:
239 /* allow flash to settle - wait 10 ms */
Simon Glassdbd79542020-05-10 11:40:11 -0600240 mdelay(10);
wdenkc4cbd342005-01-09 18:21:42 +0000241
242 if (iflag)
Simon Glassf87959b2019-11-14 12:57:40 -0700243 enable_interrupts();
wdenkc4cbd342005-01-09 18:21:42 +0000244
245 if (cflag)
Simon Glassfbf091b2019-11-14 12:57:36 -0700246 icache_enable();
wdenkc4cbd342005-01-09 18:21:42 +0000247
248 return rc;
249}
250
Simon Glassc7443162020-05-10 11:39:53 -0600251static int write_word(flash_info_t *info, ulong dest, ulong data)
wdenkc4cbd342005-01-09 18:21:42 +0000252{
253 volatile u16 *addr = (volatile u16 *) dest;
254 ulong result;
Jerome Forissier523bc4d2024-09-11 11:58:15 +0200255 int rc = FL_ERR_OK;
wdenkc4cbd342005-01-09 18:21:42 +0000256 int cflag, iflag;
257 int chip1;
Graeme Russ43f02552011-06-28 01:40:55 +0000258 ulong start;
wdenkc4cbd342005-01-09 18:21:42 +0000259
260 /*
261 * Check if Flash is (sufficiently) erased
262 */
263 result = *addr;
264 if ((result & data) != data)
Jerome Forissier523bc4d2024-09-11 11:58:15 +0200265 return FL_ERR_NOT_ERASED;
wdenkc4cbd342005-01-09 18:21:42 +0000266
wdenkc4cbd342005-01-09 18:21:42 +0000267 /*
268 * Disable interrupts which might cause a timeout
269 * here. Remember that our exception vectors are
270 * at address 0 in the flash, and we don't want a
271 * (ticker) exception to happen while the flash
272 * chip is in programming mode.
273 */
274
Simon Glassfbf091b2019-11-14 12:57:36 -0700275 cflag = icache_status();
276 icache_disable();
Simon Glassf87959b2019-11-14 12:57:40 -0700277 iflag = disable_interrupts();
wdenkc4cbd342005-01-09 18:21:42 +0000278
279 MEM_FLASH_ADDR1 = CMD_UNLOCK1;
280 MEM_FLASH_ADDR2 = CMD_UNLOCK2;
281 MEM_FLASH_ADDR1 = CMD_PROGRAM;
282 *addr = data;
283
284 /* arm simple, non interrupt dependent timer */
Graeme Russ43f02552011-06-28 01:40:55 +0000285 start = get_timer(0);
wdenkc4cbd342005-01-09 18:21:42 +0000286
287 /* wait until flash is ready */
288 chip1 = 0;
289 do {
290 result = *addr;
291
Tom Rini78f88002022-07-23 13:05:00 -0400292 /* check timeout, 1000ms */
293 if (get_timer(start) > 1000) {
wdenkc4cbd342005-01-09 18:21:42 +0000294 chip1 = ERR | TMO;
295 break;
296 }
297 if (!chip1 && ((result & 0x80) == (data & 0x80)))
298 chip1 = READY;
299
300 } while (!chip1);
301
302 *addr = CMD_READ_ARRAY;
303
304 if (chip1 == ERR || *addr != data)
Jerome Forissier523bc4d2024-09-11 11:58:15 +0200305 rc = FL_ERR_PROG_ERROR;
wdenkc4cbd342005-01-09 18:21:42 +0000306
307 if (iflag)
Simon Glassf87959b2019-11-14 12:57:40 -0700308 enable_interrupts();
wdenkc4cbd342005-01-09 18:21:42 +0000309
310 if (cflag)
Simon Glassfbf091b2019-11-14 12:57:36 -0700311 icache_enable();
wdenkc4cbd342005-01-09 18:21:42 +0000312
313 return rc;
314}
315
Simon Glassc7443162020-05-10 11:39:53 -0600316int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
wdenkc4cbd342005-01-09 18:21:42 +0000317{
318 ulong wp, data;
319 int rc;
320
321 if (addr & 1) {
322 printf ("unaligned destination not supported\n");
Jerome Forissier523bc4d2024-09-11 11:58:15 +0200323 return FL_ERR_ALIGN;
wdenkc4cbd342005-01-09 18:21:42 +0000324 }
325
326#if 0
327 if (cnt & 1) {
328 printf ("odd transfer sizes not supported\n");
Jerome Forissier523bc4d2024-09-11 11:58:15 +0200329 return FL_ERR_ALIGN;
wdenkc4cbd342005-01-09 18:21:42 +0000330 }
331#endif
332
333 wp = addr;
334
335 if (addr & 1) {
336 data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
337 src);
338 if ((rc = write_word (info, wp - 1, data)) != 0) {
339 return (rc);
340 }
341 src += 1;
342 wp += 1;
343 cnt -= 1;
344 }
345
346 while (cnt >= 2) {
347 data = *((volatile u16 *) src);
348 if ((rc = write_word (info, wp, data)) != 0) {
349 return (rc);
350 }
351 src += 2;
352 wp += 2;
353 cnt -= 2;
354 }
355
356 if (cnt == 1) {
357 data = (*((volatile u8 *) src) << 8) |
358 *((volatile u8 *) (wp + 1));
359 if ((rc = write_word (info, wp, data)) != 0) {
360 return (rc);
361 }
362 src += 1;
363 wp += 1;
364 cnt -= 1;
365 }
366
Jerome Forissier523bc4d2024-09-11 11:58:15 +0200367 return FL_ERR_OK;
wdenkc4cbd342005-01-09 18:21:42 +0000368}