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git01.mediatek.com / filogic / uboot / 5b6b18eae44a80caafc4c41531cdae86e5bdf915 / . / arch / arm / dts / dra72-evm-revc.dts
blob: bc814f1b4cad9610252fbbc9c85cc0299527ffde [file] [log] [blame]
Mugunthan V Nb8c6b022016-09-27 13:01:41 +0530[diff] [blame]1/*
2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8#include "dra72-evm-common.dtsi"
9#include <dt-bindings/net/ti-dp83867.h>
10
11/ {
12 model = "TI DRA722 Rev C EVM";
13
Lokesh Vutlada047422016-11-23 13:25:29 +0530[diff] [blame]14 memory@0 {
Mugunthan V Nb8c6b022016-09-27 13:01:41 +0530[diff] [blame]15 device_type = "memory";
16 reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
17 };
18};
19
Lokesh Vutlada047422016-11-23 13:25:29 +0530[diff] [blame]20&i2c1 {
21 tps65917: tps65917@58 {
22 reg = <0x58>;
23
24 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
Mugunthan V Nb8c6b022016-09-27 13:01:41 +0530[diff] [blame]25 };
26};
27
Lokesh Vutlada047422016-11-23 13:25:29 +0530[diff] [blame]28#include "dra72-evm-tps65917.dtsi"
29
30&ldo2_reg {
31 /* LDO2_OUT --> VDDA_1V8_PHY2 */
32 regulator-always-on;
33 regulator-boot-on;
34};
35
Mugunthan V Nb8c6b022016-09-27 13:01:41 +0530[diff] [blame]36&hdmi {
Lokesh Vutlada047422016-11-23 13:25:29 +0530[diff] [blame]37 vdda-supply = <&ldo2_reg>;
38};
39
40&pcf_gpio_21 {
41 interrupt-parent = <&gpio3>;
42 interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
Mugunthan V Nb8c6b022016-09-27 13:01:41 +0530[diff] [blame]43};
44
45&mac {
46 mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
47 <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */
48 <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */
49 dual_emac;
50};
51
52&cpsw_emac0 {
53 phy-handle = <&dp83867_0>;
54 phy-mode = "rgmii-id";
55 dual_emac_res_vlan = <1>;
56};
57
58&cpsw_emac1 {
59 phy-handle = <&dp83867_1>;
60 phy-mode = "rgmii-id";
61 dual_emac_res_vlan = <2>;
62};
63
64&davinci_mdio {
65 dp83867_0: ethernet-phy@2 {
66 reg = <2>;
67 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
68 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
69 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
Mugunthan V N5b6b18e2017-01-24 11:15:40 -0600[diff] [blame^]70 ti,min-output-impedance;
Mugunthan V Nb8c6b022016-09-27 13:01:41 +0530[diff] [blame]71 };
72
73 dp83867_1: ethernet-phy@3 {
74 reg = <3>;
75 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
76 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
77 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
Mugunthan V N5b6b18e2017-01-24 11:15:40 -0600[diff] [blame^]78 ti,min-output-impedance;
Mugunthan V Nb8c6b022016-09-27 13:01:41 +0530[diff] [blame]79 };
80};