Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 1 | /* |
| 2 | * am3517_crane.h - Default configuration for AM3517 CraneBoard. |
| 3 | * |
| 4 | * Author: Srinath.R <srinath@mistralsolutions.com> |
| 5 | * |
| 6 | * Based on include/configs/am3517evm.h |
| 7 | * |
| 8 | * Copyright (C) 2011 Mistral Solutions pvt Ltd |
| 9 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 10 | * SPDX-License-Identifier: GPL-2.0+ |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | #ifndef __CONFIG_H |
| 14 | #define __CONFIG_H |
| 15 | |
| 16 | /* |
| 17 | * High Level Configuration Options |
| 18 | */ |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 19 | #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ |
| 20 | |
| 21 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
Nishanth Menon | fa96c96 | 2015-03-09 17:12:04 -0500 | [diff] [blame] | 22 | #include <asm/arch/omap.h> |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 23 | |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 24 | /* Clock Defines */ |
| 25 | #define V_OSCK 26000000 /* Clock output from T2 */ |
| 26 | #define V_SCLK (V_OSCK >> 1) |
| 27 | |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 28 | #define CONFIG_MISC_INIT_R |
| 29 | |
| 30 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
| 31 | #define CONFIG_SETUP_MEMORY_TAGS 1 |
| 32 | #define CONFIG_INITRD_TAG 1 |
| 33 | #define CONFIG_REVISION_TAG 1 |
| 34 | |
| 35 | /* |
| 36 | * Size of malloc() pool |
| 37 | */ |
| 38 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ |
| 39 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) |
| 40 | /* initial data */ |
| 41 | /* |
| 42 | * DDR related |
| 43 | */ |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 44 | #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) |
| 45 | |
| 46 | /* |
| 47 | * Hardware drivers |
| 48 | */ |
| 49 | |
| 50 | /* |
| 51 | * NS16550 Configuration |
| 52 | */ |
| 53 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ |
| 54 | |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 55 | #define CONFIG_SYS_NS16550_SERIAL |
| 56 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) |
| 57 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
| 58 | |
| 59 | /* |
| 60 | * select serial console configuration |
| 61 | */ |
| 62 | #define CONFIG_CONS_INDEX 3 |
| 63 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 |
| 64 | #define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */ |
| 65 | |
| 66 | /* allow to overwrite serial and ethaddr */ |
| 67 | #define CONFIG_ENV_OVERWRITE |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 68 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ |
| 69 | 115200} |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 70 | |
| 71 | /* |
| 72 | * USB configuration |
Paul Kocialkowski | f34dfcb | 2015-08-04 17:04:06 +0200 | [diff] [blame] | 73 | * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard |
| 74 | * Enable CONFIG_USB_MUSB_UDC for Device functionalities. |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 75 | */ |
| 76 | #define CONFIG_USB_AM35X 1 |
Paul Kocialkowski | f34dfcb | 2015-08-04 17:04:06 +0200 | [diff] [blame] | 77 | #define CONFIG_USB_MUSB_HCD 1 |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 78 | |
| 79 | #ifdef CONFIG_USB_AM35X |
| 80 | |
Paul Kocialkowski | f34dfcb | 2015-08-04 17:04:06 +0200 | [diff] [blame] | 81 | #ifdef CONFIG_USB_MUSB_HCD |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 82 | |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 83 | #ifdef CONFIG_USB_KEYBOARD |
| 84 | #define CONFIG_SYS_USB_EVENT_POLL |
| 85 | #define CONFIG_PREBOOT "usb start" |
| 86 | #endif /* CONFIG_USB_KEYBOARD */ |
| 87 | |
Paul Kocialkowski | f34dfcb | 2015-08-04 17:04:06 +0200 | [diff] [blame] | 88 | #endif /* CONFIG_USB_MUSB_HCD */ |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 89 | |
Paul Kocialkowski | f34dfcb | 2015-08-04 17:04:06 +0200 | [diff] [blame] | 90 | #ifdef CONFIG_USB_MUSB_UDC |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 91 | /* USB device configuration */ |
| 92 | #define CONFIG_USB_DEVICE 1 |
| 93 | #define CONFIG_USB_TTY 1 |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 94 | /* Change these to suit your needs */ |
| 95 | #define CONFIG_USBD_VENDORID 0x0451 |
| 96 | #define CONFIG_USBD_PRODUCTID 0x5678 |
| 97 | #define CONFIG_USBD_MANUFACTURER "Texas Instruments" |
| 98 | #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" |
Paul Kocialkowski | f34dfcb | 2015-08-04 17:04:06 +0200 | [diff] [blame] | 99 | #endif /* CONFIG_USB_MUSB_UDC */ |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 100 | |
| 101 | #endif /* CONFIG_USB_AM35X */ |
| 102 | |
Heiko Schocher | f53f2b8 | 2013-10-22 11:03:18 +0200 | [diff] [blame] | 103 | #define CONFIG_SYS_I2C |
| 104 | #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 |
| 105 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 |
| 106 | #define CONFIG_SYS_I2C_OMAP34XX |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 107 | |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 108 | /* |
| 109 | * Board NAND Info. |
| 110 | */ |
| 111 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ |
| 112 | /* to access nand */ |
| 113 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ |
| 114 | /* to access */ |
| 115 | /* nand at CS0 */ |
| 116 | |
| 117 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ |
| 118 | /* NAND devices */ |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 119 | |
| 120 | #define CONFIG_JFFS2_NAND |
| 121 | /* nand device jffs2 lives on */ |
| 122 | #define CONFIG_JFFS2_DEV "nand0" |
| 123 | /* start of jffs2 partition */ |
| 124 | #define CONFIG_JFFS2_PART_OFFSET 0x680000 |
| 125 | #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ |
| 126 | |
| 127 | /* Environment information */ |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 128 | |
Joe Hershberger | e4da248 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 129 | #define CONFIG_BOOTFILE "uImage" |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 130 | |
| 131 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 132 | "loadaddr=0x82000000\0" \ |
| 133 | "console=ttyS2,115200n8\0" \ |
Tom Rini | 54c0b7b | 2011-09-03 21:51:50 -0400 | [diff] [blame] | 134 | "mmcdev=0\0" \ |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 135 | "mmcargs=setenv bootargs console=${console} " \ |
| 136 | "root=/dev/mmcblk0p2 rw " \ |
| 137 | "rootfstype=ext3 rootwait\0" \ |
| 138 | "nandargs=setenv bootargs console=${console} " \ |
| 139 | "root=/dev/mtdblock4 rw " \ |
| 140 | "rootfstype=jffs2\0" \ |
Tom Rini | 54c0b7b | 2011-09-03 21:51:50 -0400 | [diff] [blame] | 141 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 142 | "bootscript=echo Running bootscript from mmc ...; " \ |
| 143 | "source ${loadaddr}\0" \ |
Tom Rini | 54c0b7b | 2011-09-03 21:51:50 -0400 | [diff] [blame] | 144 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 145 | "mmcboot=echo Booting from mmc ...; " \ |
| 146 | "run mmcargs; " \ |
| 147 | "bootm ${loadaddr}\0" \ |
| 148 | "nandboot=echo Booting from nand ...; " \ |
| 149 | "run nandargs; " \ |
| 150 | "nand read ${loadaddr} 280000 400000; " \ |
| 151 | "bootm ${loadaddr}\0" \ |
| 152 | |
| 153 | #define CONFIG_BOOTCOMMAND \ |
Andrew Bradford | e1c7c8a | 2012-10-01 05:06:52 +0000 | [diff] [blame] | 154 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 155 | "if run loadbootscript; then " \ |
| 156 | "run bootscript; " \ |
| 157 | "else " \ |
| 158 | "if run loaduimage; then " \ |
| 159 | "run mmcboot; " \ |
| 160 | "else run nandboot; " \ |
| 161 | "fi; " \ |
| 162 | "fi; " \ |
| 163 | "else run nandboot; fi" |
| 164 | |
| 165 | #define CONFIG_AUTO_COMPLETE 1 |
| 166 | /* |
| 167 | * Miscellaneous configurable options |
| 168 | */ |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 169 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 170 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
| 171 | /* Print Buffer Size */ |
| 172 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| 173 | sizeof(CONFIG_SYS_PROMPT) + 16) |
| 174 | #define CONFIG_SYS_MAXARGS 32 /* max number of command */ |
| 175 | /* args */ |
| 176 | /* Boot Argument Buffer Size */ |
| 177 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) |
| 178 | /* memtest works on */ |
| 179 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) |
| 180 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ |
| 181 | 0x01F00000) /* 31MB */ |
| 182 | |
| 183 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ |
| 184 | /* address */ |
| 185 | |
| 186 | /* |
| 187 | * AM3517 has 12 GP timers, they can be driven by the system clock |
| 188 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). |
| 189 | * This rate is divided by a local divisor. |
| 190 | */ |
| 191 | #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 |
| 192 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 193 | |
| 194 | /*----------------------------------------------------------------------- |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 195 | * Physical Memory Map |
| 196 | */ |
| 197 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ |
| 198 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 199 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
| 200 | |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 201 | /*----------------------------------------------------------------------- |
| 202 | * FLASH and environment organization |
| 203 | */ |
| 204 | |
| 205 | /* **** PISMO SUPPORT *** */ |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 206 | #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ |
| 207 | /* on one chip */ |
| 208 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ |
| 209 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
| 210 | |
pekon gupta | 0a9ec45 | 2014-07-18 17:59:41 +0530 | [diff] [blame] | 211 | #define CONFIG_SYS_FLASH_BASE NAND_BASE |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 212 | |
| 213 | /* Monitor at start of flash */ |
| 214 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| 215 | |
| 216 | #define CONFIG_NAND_OMAP_GPMC |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 217 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ |
| 218 | |
Luca Ceresoli | 9783a2c | 2011-04-20 11:02:05 -0400 | [diff] [blame] | 219 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ |
| 220 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET |
| 221 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 222 | |
| 223 | /*----------------------------------------------------------------------- |
| 224 | * CFI FLASH driver setup |
| 225 | */ |
| 226 | /* timeout values are in ticks */ |
| 227 | #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) |
| 228 | #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) |
| 229 | |
| 230 | /* Flash banks JFFS2 should use */ |
| 231 | #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ |
| 232 | CONFIG_SYS_MAX_NAND_DEVICE) |
| 233 | #define CONFIG_SYS_JFFS2_MEM_NAND |
| 234 | /* use flash_info[2] */ |
| 235 | #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS |
| 236 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 |
| 237 | |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 238 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 239 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 |
| 240 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 |
| 241 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 242 | CONFIG_SYS_INIT_RAM_SIZE - \ |
| 243 | GENERATED_GBL_DATA_SIZE) |
Tom Rini | 9e34185 | 2011-11-18 12:48:11 +0000 | [diff] [blame] | 244 | |
| 245 | /* Defines for SPL */ |
Tom Rini | 28591df | 2012-08-13 12:03:19 -0700 | [diff] [blame] | 246 | #define CONFIG_SPL_FRAMEWORK |
Tom Rini | 9e34185 | 2011-11-18 12:48:11 +0000 | [diff] [blame] | 247 | #define CONFIG_SPL_NAND_SIMPLE |
| 248 | #define CONFIG_SPL_TEXT_BASE 0x40200800 |
Tom Rini | cfff4aa | 2016-08-26 13:30:43 -0400 | [diff] [blame] | 249 | #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ |
| 250 | CONFIG_SPL_TEXT_BASE) |
Tom Rini | 9e34185 | 2011-11-18 12:48:11 +0000 | [diff] [blame] | 251 | |
| 252 | #define CONFIG_SPL_BSS_START_ADDR 0x80000000 |
| 253 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ |
| 254 | |
Paul Kocialkowski | 341e8cd | 2014-11-08 23:14:55 +0100 | [diff] [blame] | 255 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
Guillaume GARDET | 602a16c | 2014-10-15 17:53:11 +0200 | [diff] [blame] | 256 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
Tom Rini | 9e34185 | 2011-11-18 12:48:11 +0000 | [diff] [blame] | 257 | |
Scott Wood | c352a0c | 2012-09-20 19:09:07 -0500 | [diff] [blame] | 258 | #define CONFIG_SPL_NAND_BASE |
| 259 | #define CONFIG_SPL_NAND_DRIVERS |
| 260 | #define CONFIG_SPL_NAND_ECC |
Tom Rini | 28eec37 | 2016-11-07 21:34:54 -0500 | [diff] [blame] | 261 | #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" |
Tom Rini | 9e34185 | 2011-11-18 12:48:11 +0000 | [diff] [blame] | 262 | |
| 263 | /* NAND boot config */ |
Stefano Babic | 0cd4118 | 2015-07-26 15:18:15 +0200 | [diff] [blame] | 264 | #define CONFIG_SYS_NAND_BUSWIDTH_16BIT |
Tom Rini | 9e34185 | 2011-11-18 12:48:11 +0000 | [diff] [blame] | 265 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
| 266 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 |
| 267 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 |
| 268 | #define CONFIG_SYS_NAND_OOBSIZE 64 |
| 269 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) |
| 270 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS |
| 271 | #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ |
| 272 | 10, 11, 12, 13} |
| 273 | #define CONFIG_SYS_NAND_ECCSIZE 512 |
| 274 | #define CONFIG_SYS_NAND_ECCBYTES 3 |
pekon gupta | 3ef4973 | 2013-11-18 19:03:01 +0530 | [diff] [blame] | 275 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW |
Tom Rini | 9e34185 | 2011-11-18 12:48:11 +0000 | [diff] [blame] | 276 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE |
| 277 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 |
| 278 | |
| 279 | /* |
| 280 | * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM |
| 281 | * 64 bytes before this address should be set aside for u-boot.img's |
| 282 | * header. That is 0x800FFFC0--0x80100000 should not be used for any |
| 283 | * other needs. |
| 284 | */ |
| 285 | #define CONFIG_SYS_TEXT_BASE 0x80100000 |
| 286 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 |
| 287 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 |
| 288 | |
Srinath | 714194e | 2011-04-18 17:40:35 -0400 | [diff] [blame] | 289 | #endif /* __CONFIG_H */ |