Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2005 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* |
| 25 | * TQM8349 board configuration file |
| 26 | */ |
| 27 | |
| 28 | #ifndef __CONFIG_H |
| 29 | #define __CONFIG_H |
| 30 | |
| 31 | #define DEBUG |
| 32 | #undef DEBUG |
| 33 | |
| 34 | /* |
| 35 | * High Level Configuration Options |
| 36 | */ |
| 37 | #define CONFIG_E300 1 /* E300 Family */ |
| 38 | #define CONFIG_MPC83XX 1 /* MPC83XX family */ |
Tanya Jiang | 5b2c905 | 2006-08-03 18:38:13 +0800 | [diff] [blame^] | 39 | #define CONFIG_MPC8349 1 /* MPC8349 specific */ |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 40 | #define CONFIG_MPC834X 1 /* MPC834X specific */ |
| 41 | #define CONFIG_TQM834X 1 /* TQM834X board specific */ |
| 42 | |
| 43 | /* IMMR Base Addres Register, use Freescale default: 0xff400000 */ |
Marian Balakowicz | b862ccd | 2005-10-12 12:45:04 +0200 | [diff] [blame] | 44 | #define CFG_IMMRBAR 0xff400000 |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 45 | |
| 46 | /* System clock. Primary input clock when in PCI host mode */ |
| 47 | #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ |
| 48 | |
| 49 | /* |
| 50 | * Local Bus LCRR |
| 51 | * LCRR: DLL bypass, Clock divider is 8 |
| 52 | * |
| 53 | * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz |
| 54 | * |
| 55 | * External Local Bus rate is |
| 56 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV |
| 57 | */ |
| 58 | #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) |
| 59 | |
Tanya Jiang | 5b2c905 | 2006-08-03 18:38:13 +0800 | [diff] [blame^] | 60 | #define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK)) |
| 61 | #define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */ |
| 62 | #define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */ |
| 63 | #define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */ |
| 64 | #define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */ |
| 65 | #define CFG_SCCR_VAL ( CFG_SCCR_INIT \ |
| 66 | | CFG_SCCR_TSEC1CM \ |
| 67 | | CFG_SCCR_TSEC2CM \ |
| 68 | | CFG_SCCR_ENCCM \ |
| 69 | | CFG_SCCR_USBCM ) |
| 70 | |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 71 | /* board pre init: do not call, nothing to do */ |
| 72 | #undef CONFIG_BOARD_EARLY_INIT_F |
| 73 | |
| 74 | /* detect the number of flash banks */ |
| 75 | #define CONFIG_BOARD_EARLY_INIT_R |
| 76 | |
| 77 | /* |
| 78 | * DDR Setup |
| 79 | */ |
| 80 | #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ |
| 81 | #define CFG_SDRAM_BASE CFG_DDR_BASE |
| 82 | #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE |
| 83 | #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ |
| 84 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
| 85 | #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ |
| 86 | |
| 87 | #undef CFG_DRAM_TEST /* memory test, takes time */ |
| 88 | #define CFG_MEMTEST_START 0x00000000 /* memtest region */ |
| 89 | #define CFG_MEMTEST_END 0x00100000 |
| 90 | |
| 91 | /* |
| 92 | * FLASH on the Local Bus |
| 93 | */ |
| 94 | #define CFG_FLASH_CFI /* use the Common Flash Interface */ |
| 95 | #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ |
| 96 | #undef CFG_FLASH_CHECKSUM |
| 97 | #define CFG_FLASH_BASE 0x80000000 /* start of FLASH */ |
| 98 | |
| 99 | /* buffered writes in the AMD chip set is not supported yet */ |
| 100 | #undef CFG_FLASH_USE_BUFFER_WRITE |
| 101 | |
| 102 | /* |
| 103 | * FLASH bank number detection |
| 104 | */ |
| 105 | |
| 106 | /* |
| 107 | * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash |
| 108 | * banks has to be determined at runtime and stored in a gloabl variable |
| 109 | * tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only |
Wolfgang Denk | f6a692b | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 110 | * used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 111 | * should be made sufficiently large to accomodate the number of banks that |
Wolfgang Denk | f6a692b | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 112 | * might actually be detected. Since most (all?) Flash related functions use |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 113 | * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is |
| 114 | * defined as tqm834x_num_flash_banks. |
| 115 | */ |
| 116 | #define CFG_MAX_FLASH_BANKS_DETECT 2 |
Wolfgang Denk | f6a692b | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 117 | #ifndef __ASSEMBLY__ |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 118 | extern int tqm834x_num_flash_banks; |
| 119 | #endif |
| 120 | #define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks) |
| 121 | |
| 122 | #define CFG_MAX_FLASH_SECT 512 /* max sectors per device */ |
| 123 | |
| 124 | /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ |
| 125 | #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA) | \ |
| 126 | BR_MS_GPCM | BR_PS_32 | BR_V) |
| 127 | |
| 128 | /* FLASH timing (0x0000_0c54) */ |
| 129 | #define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \ |
| 130 | OR_GPCM_SCY_5 | OR_GPCM_TRLX) |
| 131 | |
| 132 | #define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */ |
| 133 | |
| 134 | #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) |
| 135 | |
| 136 | #define CFG_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */ |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 137 | |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 138 | #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ |
| 139 | |
| 140 | /* disable remaining mappings */ |
| 141 | #define CFG_BR1_PRELIM 0x00000000 |
| 142 | #define CFG_OR1_PRELIM 0x00000000 |
| 143 | #define CFG_LBLAWBAR1_PRELIM 0x00000000 |
| 144 | #define CFG_LBLAWAR1_PRELIM 0x00000000 |
| 145 | |
| 146 | #define CFG_BR2_PRELIM 0x00000000 |
| 147 | #define CFG_OR2_PRELIM 0x00000000 |
| 148 | #define CFG_LBLAWBAR2_PRELIM 0x00000000 |
| 149 | #define CFG_LBLAWAR2_PRELIM 0x00000000 |
| 150 | |
| 151 | #define CFG_BR3_PRELIM 0x00000000 |
| 152 | #define CFG_OR3_PRELIM 0x00000000 |
| 153 | #define CFG_LBLAWBAR3_PRELIM 0x00000000 |
| 154 | #define CFG_LBLAWAR3_PRELIM 0x00000000 |
| 155 | |
| 156 | #define CFG_BR4_PRELIM 0x00000000 |
| 157 | #define CFG_OR4_PRELIM 0x00000000 |
| 158 | #define CFG_LBLAWBAR4_PRELIM 0x00000000 |
| 159 | #define CFG_LBLAWAR4_PRELIM 0x00000000 |
| 160 | |
| 161 | #define CFG_BR5_PRELIM 0x00000000 |
| 162 | #define CFG_OR5_PRELIM 0x00000000 |
| 163 | #define CFG_LBLAWBAR5_PRELIM 0x00000000 |
| 164 | #define CFG_LBLAWAR5_PRELIM 0x00000000 |
| 165 | |
| 166 | #define CFG_BR6_PRELIM 0x00000000 |
| 167 | #define CFG_OR6_PRELIM 0x00000000 |
| 168 | #define CFG_LBLAWBAR6_PRELIM 0x00000000 |
| 169 | #define CFG_LBLAWAR6_PRELIM 0x00000000 |
| 170 | |
| 171 | #define CFG_BR7_PRELIM 0x00000000 |
| 172 | #define CFG_OR7_PRELIM 0x00000000 |
| 173 | #define CFG_LBLAWBAR7_PRELIM 0x00000000 |
| 174 | #define CFG_LBLAWAR7_PRELIM 0x00000000 |
| 175 | |
| 176 | /* |
| 177 | * Monitor config |
| 178 | */ |
| 179 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
| 180 | |
| 181 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
| 182 | #define CFG_RAMBOOT |
| 183 | #else |
| 184 | #undef CFG_RAMBOOT |
| 185 | #endif |
| 186 | |
| 187 | #define CONFIG_L1_INIT_RAM |
| 188 | #define CFG_INIT_RAM_LOCK 1 |
| 189 | #define CFG_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ |
| 190 | #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ |
| 191 | |
| 192 | #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
| 193 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
| 194 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
| 195 | |
| 196 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 197 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
| 198 | |
| 199 | /* |
| 200 | * Serial Port |
| 201 | */ |
| 202 | #define CONFIG_CONS_INDEX 1 |
| 203 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
| 204 | #define CFG_NS16550 |
| 205 | #define CFG_NS16550_SERIAL |
| 206 | #define CFG_NS16550_REG_SIZE 1 |
| 207 | #define CFG_NS16550_CLK get_bus_freq(0) |
| 208 | |
| 209 | #define CFG_BAUDRATE_TABLE \ |
| 210 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 211 | |
| 212 | #define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500) |
| 213 | #define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600) |
| 214 | |
| 215 | /* |
| 216 | * I2C |
| 217 | */ |
| 218 | #define CONFIG_HARD_I2C /* I2C with hardware support */ |
| 219 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
| 220 | #define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */ |
| 221 | #define CFG_I2C_SLAVE 0x7F /* slave address */ |
| 222 | #define CFG_I2C_OFFSET 0x3000 |
| 223 | |
| 224 | /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ |
| 225 | #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
| 226 | #define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ |
| 227 | #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */ |
| 228 | #define CFG_EEPROM_PAGE_WRITE_ENABLE |
| 229 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ |
| 230 | #define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ |
| 231 | |
| 232 | /* I2C RTC */ |
| 233 | #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ |
| 234 | #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
| 235 | |
| 236 | /* I2C SYSMON (LM75) */ |
| 237 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ |
| 238 | #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ |
| 239 | #define CFG_DTT_MAX_TEMP 70 |
| 240 | #define CFG_DTT_LOW_TEMP -30 |
| 241 | #define CFG_DTT_HYSTERESIS 3 |
| 242 | |
| 243 | /* |
| 244 | * TSEC |
| 245 | */ |
| 246 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
| 247 | #define CONFIG_MII |
| 248 | |
| 249 | #define CFG_TSEC1_OFFSET 0x24000 |
| 250 | #define CFG_TSEC1 (CFG_IMMRBAR + CFG_TSEC1_OFFSET) |
| 251 | #define CFG_TSEC2_OFFSET 0x25000 |
| 252 | #define CFG_TSEC2 (CFG_IMMRBAR + CFG_TSEC2_OFFSET) |
| 253 | |
| 254 | #if defined(CONFIG_TSEC_ENET) |
| 255 | |
| 256 | #ifndef CONFIG_NET_MULTI |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 257 | #define CONFIG_NET_MULTI |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 258 | #endif |
| 259 | |
| 260 | #define CONFIG_MPC83XX_TSEC1 1 |
| 261 | #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" |
| 262 | #define CONFIG_MPC83XX_TSEC2 1 |
| 263 | #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" |
Wolfgang Denk | 626a55a | 2005-12-01 01:17:24 +0100 | [diff] [blame] | 264 | #define TSEC1_PHY_ADDR 2 |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 265 | #define TSEC2_PHY_ADDR 1 |
| 266 | #define TSEC1_PHYIDX 0 |
| 267 | #define TSEC2_PHYIDX 0 |
| 268 | |
| 269 | /* Options are: TSEC[0-1] */ |
| 270 | #define CONFIG_ETHPRIME "TSEC0" |
| 271 | |
| 272 | #endif /* CONFIG_TSEC_ENET */ |
| 273 | |
| 274 | /* |
| 275 | * General PCI |
| 276 | * Addresses are mapped 1-1. |
| 277 | */ |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 278 | #define CONFIG_PCI |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 279 | |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 280 | #if defined(CONFIG_PCI) |
| 281 | |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 282 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 283 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 284 | |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 285 | /* PCI1 host bridge */ |
| 286 | #define CFG_PCI1_MEM_BASE 0xc0000000 |
| 287 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
| 288 | #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
| 289 | #define CFG_PCI1_IO_BASE 0xe2000000 |
| 290 | #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE |
| 291 | #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ |
| 292 | |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 293 | |
| 294 | #undef CONFIG_EEPRO100 |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 295 | #define CONFIG_EEPRO100 |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 296 | #undef CONFIG_TULIP |
| 297 | |
| 298 | #if !defined(CONFIG_PCI_PNP) |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 299 | #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE |
| 300 | #define PCI_ENET0_MEMADDR CFG_PCI1_MEM_BASE |
| 301 | #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 302 | #endif |
| 303 | |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 304 | #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 305 | |
| 306 | #endif /* CONFIG_PCI */ |
| 307 | |
| 308 | /* |
| 309 | * Environment |
| 310 | */ |
| 311 | #define CONFIG_ENV_OVERWRITE |
| 312 | |
| 313 | #ifndef CFG_RAMBOOT |
| 314 | #define CFG_ENV_IS_IN_FLASH 1 |
| 315 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
| 316 | #define CFG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ |
| 317 | #define CFG_ENV_SIZE 0x2000 |
| 318 | #else |
| 319 | #define CFG_NO_FLASH 1 /* Flash is not usable now */ |
| 320 | #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
| 321 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
| 322 | #define CFG_ENV_SIZE 0x2000 |
| 323 | #endif |
| 324 | |
| 325 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 326 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 327 | |
| 328 | /* Common commands */ |
| 329 | #define CFG_CMD_TQM8349_COMMON CFG_CMD_DATE | CFG_CMD_I2C | CFG_CMD_DTT\ |
| 330 | | CFG_CMD_PING | CFG_CMD_EEPROM \ |
| 331 | | CFG_CMD_MII | CFG_CMD_JFFS2 |
| 332 | |
| 333 | #if defined(CFG_RAMBOOT) |
| 334 | |
| 335 | #if defined(CONFIG_PCI) |
| 336 | #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI \ |
| 337 | | CFG_CMD_TQM8349_COMMON) \ |
| 338 | & \ |
| 339 | ~(CFG_CMD_ENV | CFG_CMD_LOADS)) |
| 340 | #else |
| 341 | #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ |
| 342 | | CFG_CMD_TQM8349_COMMON) \ |
| 343 | & \ |
| 344 | ~(CFG_CMD_ENV | CFG_CMD_LOADS)) |
| 345 | #endif |
| 346 | |
| 347 | #else /* CFG_RAMBOOT */ |
| 348 | |
| 349 | #if defined(CONFIG_PCI) |
| 350 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \ |
| 351 | | CFG_CMD_TQM8349_COMMON) |
| 352 | #else |
| 353 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
| 354 | | CFG_CMD_TQM8349_COMMON) |
| 355 | #endif |
| 356 | |
| 357 | #endif /* CFG_RAMBOOT */ |
| 358 | |
| 359 | #include <cmd_confdefs.h> |
| 360 | |
| 361 | /* |
| 362 | * Miscellaneous configurable options |
| 363 | */ |
| 364 | #define CFG_LONGHELP /* undef to save memory */ |
| 365 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
| 366 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
| 367 | |
Wolfgang Denk | 274bac5 | 2006-10-28 02:29:14 +0200 | [diff] [blame] | 368 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
| 369 | #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ |
| 370 | #ifdef CFG_HUSH_PARSER |
| 371 | #define CFG_PROMPT_HUSH_PS2 "> " |
| 372 | #endif |
| 373 | |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 374 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 375 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 376 | #else |
| 377 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
| 378 | #endif |
| 379 | |
| 380 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| 381 | #define CFG_MAXARGS 16 /* max number of command args */ |
| 382 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 383 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
| 384 | |
| 385 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 386 | |
| 387 | /* |
| 388 | * For booting Linux, the board info and command line data |
| 389 | * have to be in the first 8 MB of memory, since this is |
| 390 | * the maximum mapped by the Linux kernel during initialization. |
| 391 | */ |
| 392 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
| 393 | |
| 394 | /* |
| 395 | * Cache Configuration |
| 396 | */ |
| 397 | #define CFG_DCACHE_SIZE 32768 |
| 398 | #define CFG_CACHELINE_SIZE 32 |
| 399 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 400 | #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
| 401 | #endif |
| 402 | |
| 403 | #define CFG_HRCW_LOW (\ |
| 404 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 405 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ |
| 406 | HRCWL_CSB_TO_CLKIN_4X1 |\ |
| 407 | HRCWL_VCO_1X2 |\ |
| 408 | HRCWL_CORE_TO_CSB_2X1) |
| 409 | |
| 410 | #if defined(PCI_64BIT) |
| 411 | #define CFG_HRCW_HIGH (\ |
| 412 | HRCWH_PCI_HOST |\ |
| 413 | HRCWH_64_BIT_PCI |\ |
| 414 | HRCWH_PCI1_ARBITER_ENABLE |\ |
| 415 | HRCWH_PCI2_ARBITER_DISABLE |\ |
| 416 | HRCWH_CORE_ENABLE |\ |
| 417 | HRCWH_FROM_0X00000100 |\ |
| 418 | HRCWH_BOOTSEQ_DISABLE |\ |
| 419 | HRCWH_SW_WATCHDOG_DISABLE |\ |
| 420 | HRCWH_ROM_LOC_LOCAL_16BIT |\ |
| 421 | HRCWH_TSEC1M_IN_GMII |\ |
| 422 | HRCWH_TSEC2M_IN_GMII ) |
| 423 | #else |
| 424 | #define CFG_HRCW_HIGH (\ |
| 425 | HRCWH_PCI_HOST |\ |
| 426 | HRCWH_32_BIT_PCI |\ |
| 427 | HRCWH_PCI1_ARBITER_ENABLE |\ |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 428 | HRCWH_PCI2_ARBITER_DISABLE |\ |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 429 | HRCWH_CORE_ENABLE |\ |
| 430 | HRCWH_FROM_0X00000100 |\ |
| 431 | HRCWH_BOOTSEQ_DISABLE |\ |
| 432 | HRCWH_SW_WATCHDOG_DISABLE |\ |
| 433 | HRCWH_ROM_LOC_LOCAL_16BIT |\ |
| 434 | HRCWH_TSEC1M_IN_GMII |\ |
| 435 | HRCWH_TSEC2M_IN_GMII ) |
| 436 | #endif |
| 437 | |
Kumar Gala | e522143 | 2006-01-11 11:12:57 -0600 | [diff] [blame] | 438 | /* System IO Config */ |
| 439 | #define CFG_SICRH SICRH_TSOBI1 |
| 440 | #define CFG_SICRL SICRL_LDP_A |
| 441 | |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 442 | /* i-cache and d-cache disabled */ |
Rafal Jaworowski | 7a1e6be | 2006-08-18 10:39:11 +0200 | [diff] [blame] | 443 | #define CFG_HID0_INIT 0x000000000 |
| 444 | #define CFG_HID0_FINAL CFG_HID0_INIT |
| 445 | #define CFG_HID2 HID2_HBE |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 446 | |
Kumar Gala | d5d94d6 | 2006-02-10 15:40:06 -0600 | [diff] [blame] | 447 | /* DDR 0 - 512M */ |
| 448 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
| 449 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
| 450 | #define CFG_IBAT1L (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) |
| 451 | #define CFG_IBAT1U (CFG_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
| 452 | |
| 453 | /* stack in DCACHE @ 512M (no backing mem) */ |
| 454 | #define CFG_IBAT2L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) |
| 455 | #define CFG_IBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) |
| 456 | |
| 457 | /* PCI */ |
Rafal Jaworowski | 7a1e6be | 2006-08-18 10:39:11 +0200 | [diff] [blame] | 458 | #ifdef CONFIG_PCI |
| 459 | #define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
Kumar Gala | d5d94d6 | 2006-02-10 15:40:06 -0600 | [diff] [blame] | 460 | #define CFG_IBAT3U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
Rafal Jaworowski | 7a1e6be | 2006-08-18 10:39:11 +0200 | [diff] [blame] | 461 | #define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) |
Kumar Gala | d5d94d6 | 2006-02-10 15:40:06 -0600 | [diff] [blame] | 462 | #define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
| 463 | #define CFG_IBAT5L (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 464 | #define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP) |
Rafal Jaworowski | 7a1e6be | 2006-08-18 10:39:11 +0200 | [diff] [blame] | 465 | #else |
| 466 | #define CFG_IBAT3L (0) |
| 467 | #define CFG_IBAT3U (0) |
| 468 | #define CFG_IBAT4L (0) |
| 469 | #define CFG_IBAT4U (0) |
| 470 | #define CFG_IBAT5L (0) |
| 471 | #define CFG_IBAT5U (0) |
| 472 | #endif |
Kumar Gala | d5d94d6 | 2006-02-10 15:40:06 -0600 | [diff] [blame] | 473 | |
| 474 | /* IMMRBAR */ |
| 475 | #define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 476 | #define CFG_IBAT6U (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP) |
| 477 | |
| 478 | /* FLASH */ |
| 479 | #define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 480 | #define CFG_IBAT7U (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
| 481 | |
| 482 | #define CFG_DBAT0L CFG_IBAT0L |
| 483 | #define CFG_DBAT0U CFG_IBAT0U |
| 484 | #define CFG_DBAT1L CFG_IBAT1L |
| 485 | #define CFG_DBAT1U CFG_IBAT1U |
| 486 | #define CFG_DBAT2L CFG_IBAT2L |
| 487 | #define CFG_DBAT2U CFG_IBAT2U |
| 488 | #define CFG_DBAT3L CFG_IBAT3L |
| 489 | #define CFG_DBAT3U CFG_IBAT3U |
| 490 | #define CFG_DBAT4L CFG_IBAT4L |
| 491 | #define CFG_DBAT4U CFG_IBAT4U |
| 492 | #define CFG_DBAT5L CFG_IBAT5L |
| 493 | #define CFG_DBAT5U CFG_IBAT5U |
| 494 | #define CFG_DBAT6L CFG_IBAT6L |
| 495 | #define CFG_DBAT6U CFG_IBAT6U |
| 496 | #define CFG_DBAT7L CFG_IBAT7L |
| 497 | #define CFG_DBAT7U CFG_IBAT7U |
| 498 | |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 499 | /* |
| 500 | * Internal Definitions |
| 501 | * |
| 502 | * Boot Flags |
| 503 | */ |
| 504 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 505 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 506 | |
| 507 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 508 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
| 509 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 510 | #endif |
| 511 | |
| 512 | /* |
| 513 | * Environment Configuration |
| 514 | */ |
| 515 | |
| 516 | #if defined(CONFIG_TSEC_ENET) |
| 517 | #define CONFIG_ETHADDR D2:DA:5E:44:BC:29 |
| 518 | #define CONFIG_HAS_ETH1 |
| 519 | #define CONFIG_ETH1ADDR 1E:F3:40:21:92:53 |
| 520 | #endif |
| 521 | |
| 522 | #define CONFIG_IPADDR 192.168.205.1 |
| 523 | |
| 524 | #define CONFIG_HOSTNAME tqm8349 |
| 525 | #define CONFIG_ROOTPATH /opt/eldk/ppc_6xx |
| 526 | #define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage |
| 527 | |
| 528 | #define CONFIG_SERVERIP 192.168.1.1 |
| 529 | #define CONFIG_GATEWAYIP 192.168.1.1 |
| 530 | #define CONFIG_NETMASK 255.255.255.0 |
| 531 | |
| 532 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
| 533 | |
| 534 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
| 535 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
| 536 | |
| 537 | #define CONFIG_BAUDRATE 115200 |
| 538 | |
| 539 | #define CONFIG_PREBOOT "echo;" \ |
| 540 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ |
| 541 | "echo" |
| 542 | |
| 543 | #undef CONFIG_BOOTARGS |
| 544 | |
| 545 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 546 | "netdev=eth0\0" \ |
| 547 | "hostname=tqm83xx\0" \ |
| 548 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
Wolfgang Denk | 86eb3b7 | 2005-11-20 21:40:11 +0100 | [diff] [blame] | 549 | "nfsroot=${serverip}:${rootpath}\0" \ |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 550 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
Wolfgang Denk | 86eb3b7 | 2005-11-20 21:40:11 +0100 | [diff] [blame] | 551 | "addip=setenv bootargs ${bootargs} " \ |
| 552 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ |
| 553 | ":${hostname}:${netdev}:off panic=1\0" \ |
| 554 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 555 | "flash_nfs=run nfsargs addip addtty;" \ |
Wolfgang Denk | 86eb3b7 | 2005-11-20 21:40:11 +0100 | [diff] [blame] | 556 | "bootm ${kernel_addr}\0" \ |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 557 | "flash_self=run ramargs addip addtty;" \ |
Wolfgang Denk | 86eb3b7 | 2005-11-20 21:40:11 +0100 | [diff] [blame] | 558 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
| 559 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 560 | "bootm\0" \ |
| 561 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
| 562 | "bootfile=/tftpboot/tqm83xx/uImage\0" \ |
| 563 | "kernel_addr=80060000\0" \ |
| 564 | "ramdisk_addr=80160000\0" \ |
| 565 | "load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0" \ |
| 566 | "update=protect off 80000000 8003ffff; " \ |
| 567 | "era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \ |
| 568 | "upd=run load;run update\0" \ |
| 569 | "" |
| 570 | |
| 571 | #define CONFIG_BOOTCOMMAND "run flash_self" |
| 572 | |
| 573 | /* |
| 574 | * JFFS2 partitions |
| 575 | */ |
| 576 | /* mtdparts command line support */ |
| 577 | #define CONFIG_JFFS2_CMDLINE |
| 578 | #define MTDIDS_DEFAULT "nor0=TQM834x-0" |
| 579 | |
| 580 | /* default mtd partition table */ |
| 581 | #define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),128k(env),"\ |
| 582 | "1m(kernel),2m(initrd),"\ |
| 583 | "-(user);"\ |
| 584 | |
| 585 | #endif /* __CONFIG_H */ |