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git01.mediatek.com / filogic / uboot / 5b0b1b970687fc42890d2168c3291a46c5969994 / . / drivers / serial / ns16550.c
blob: 7e833fde5fd52e5c14be3727be740b781baf99a4 [file] [log] [blame]
wdenke85390d2002-04-01 14:29:03 +0000[diff] [blame]1/*
2 * COM1 NS16550 support
Stefan Roese88fbf932010-04-15 16:07:28 +0200[diff] [blame]3 * originally from linux source (arch/powerpc/boot/ns16550.c)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]4 * modified to use CONFIG_SYS_ISA_MEM and new defines
wdenke85390d2002-04-01 14:29:03 +0000[diff] [blame]5 */
6
7#include <config.h>
wdenke85390d2002-04-01 14:29:03 +0000[diff] [blame]8#include <ns16550.h>
Ladislav Michlcc294422010-02-01 23:34:25 +0100[diff] [blame]9#include <watchdog.h>
Graeme Russ14f06e62010-04-24 00:05:46 +1000[diff] [blame]10#include <linux/types.h>
11#include <asm/io.h>
wdenke85390d2002-04-01 14:29:03 +0000[diff] [blame]12
Detlev Zundel166fb542009-04-03 11:53:01 +0200[diff] [blame]13#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
14#define UART_MCRVAL (UART_MCR_DTR | \
15 UART_MCR_RTS) /* RTS/DTR */
16#define UART_FCRVAL (UART_FCR_FIFO_EN | \
17 UART_FCR_RXSR | \
18 UART_FCR_TXSR) /* Clear & enable FIFOs */
Graeme Russ14f06e62010-04-24 00:05:46 +1000[diff] [blame]19#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
20#define serial_out(x,y) outb(x,(ulong)y)
21#define serial_in(y) inb((ulong)y)
22#else
23#define serial_out(x,y) writeb(x,y)
24#define serial_in(y) readb(y)
25#endif
wdenke85390d2002-04-01 14:29:03 +0000[diff] [blame]26
27void NS16550_init (NS16550_t com_port, int baud_divisor)
28{
Graeme Russ14f06e62010-04-24 00:05:46 +1000[diff] [blame]29 serial_out(0x00, &com_port->ier);
Tom Rix93bed9b2009-05-31 12:44:37 +0200[diff] [blame]30#if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)
Graeme Russ14f06e62010-04-24 00:05:46 +1000[diff] [blame]31 serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]32#endif
Graeme Russ14f06e62010-04-24 00:05:46 +1000[diff] [blame]33 serial_out(UART_LCR_BKSE | UART_LCRVAL, (ulong)&com_port->lcr);
34 serial_out(0, &com_port->dll);
35 serial_out(0, &com_port->dlm);
36 serial_out(UART_LCRVAL, &com_port->lcr);
37 serial_out(UART_MCRVAL, &com_port->mcr);
38 serial_out(UART_FCRVAL, &com_port->fcr);
39 serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
40 serial_out(baud_divisor & 0xff, &com_port->dll);
41 serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
42 serial_out(UART_LCRVAL, &com_port->lcr);
Tom Rix93bed9b2009-05-31 12:44:37 +0200[diff] [blame]43#if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)
wdenkf8062712005-01-09 23:16:25 +0000[diff] [blame]44#if defined(CONFIG_APTIX)
Graeme Russ14f06e62010-04-24 00:05:46 +1000[diff] [blame]45 serial_out(3, &com_port->mdr1); /* /13 mode so Aptix 6MHz can hit 115200 */
wdenkf8062712005-01-09 23:16:25 +0000[diff] [blame]46#else
Graeme Russ14f06e62010-04-24 00:05:46 +1000[diff] [blame]47 serial_out(0, &com_port->mdr1); /* /16 is proper to hit 115200 with 48MHz */
wdenkf8062712005-01-09 23:16:25 +0000[diff] [blame]48#endif
Mike Frysingerd0e97862009-02-11 20:26:52 -0500[diff] [blame]49#endif /* CONFIG_OMAP */
wdenke85390d2002-04-01 14:29:03 +0000[diff] [blame]50}
51
Ron Madriddfa028a2009-02-18 14:30:44 -0800[diff] [blame]52#ifndef CONFIG_NS16550_MIN_FUNCTIONS
wdenke85390d2002-04-01 14:29:03 +0000[diff] [blame]53void NS16550_reinit (NS16550_t com_port, int baud_divisor)
54{
Graeme Russ14f06e62010-04-24 00:05:46 +1000[diff] [blame]55 serial_out(0x00, &com_port->ier);
56 serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
57 serial_out(0, &com_port->dll);
58 serial_out(0, &com_port->dlm);
59 serial_out(UART_LCRVAL, &com_port->lcr);
60 serial_out(UART_MCRVAL, &com_port->mcr);
61 serial_out(UART_FCRVAL, &com_port->fcr);
62 serial_out(UART_LCR_BKSE, &com_port->lcr);
63 serial_out(baud_divisor & 0xff, &com_port->dll);
64 serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
65 serial_out(UART_LCRVAL, &com_port->lcr);
wdenke85390d2002-04-01 14:29:03 +0000[diff] [blame]66}
Ron Madriddfa028a2009-02-18 14:30:44 -0800[diff] [blame]67#endif /* CONFIG_NS16550_MIN_FUNCTIONS */
wdenke85390d2002-04-01 14:29:03 +0000[diff] [blame]68
69void NS16550_putc (NS16550_t com_port, char c)
70{
Graeme Russ14f06e62010-04-24 00:05:46 +1000[diff] [blame]71 while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0);
72 serial_out(c, &com_port->thr);
wdenke85390d2002-04-01 14:29:03 +0000[diff] [blame]73}
74
Ron Madriddfa028a2009-02-18 14:30:44 -0800[diff] [blame]75#ifndef CONFIG_NS16550_MIN_FUNCTIONS
wdenke85390d2002-04-01 14:29:03 +0000[diff] [blame]76char NS16550_getc (NS16550_t com_port)
77{
Graeme Russ14f06e62010-04-24 00:05:46 +1000[diff] [blame]78 while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) {
wdenk29e7f5a2004-03-12 00:14:09 +0000[diff] [blame]79#ifdef CONFIG_USB_TTY
80 extern void usbtty_poll(void);
81 usbtty_poll();
82#endif
Ladislav Michlcc294422010-02-01 23:34:25 +0100[diff] [blame]83 WATCHDOG_RESET();
wdenk29e7f5a2004-03-12 00:14:09 +0000[diff] [blame]84 }
Graeme Russ14f06e62010-04-24 00:05:46 +1000[diff] [blame]85 return serial_in(&com_port->rbr);
wdenke85390d2002-04-01 14:29:03 +0000[diff] [blame]86}
87
88int NS16550_tstc (NS16550_t com_port)
89{
Graeme Russ14f06e62010-04-24 00:05:46 +1000[diff] [blame]90 return ((serial_in(&com_port->lsr) & UART_LSR_DR) != 0);
wdenke85390d2002-04-01 14:29:03 +0000[diff] [blame]91}
92
Ron Madriddfa028a2009-02-18 14:30:44 -0800[diff] [blame]93#endif /* CONFIG_NS16550_MIN_FUNCTIONS */