TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000-2004 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * (C) Copyright 2007 Freescale Semiconductor, Inc. |
| 6 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| 7 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 8 | * SPDX-License-Identifier: GPL-2.0+ |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #include <common.h> |
| 12 | #include <malloc.h> |
| 13 | #include <command.h> |
| 14 | #include <config.h> |
| 15 | #include <net.h> |
| 16 | #include <miiphy.h> |
| 17 | |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 18 | #undef ET_DEBUG |
| 19 | #undef MII_DEBUG |
| 20 | |
| 21 | /* Ethernet Transmit and Receive Buffers */ |
| 22 | #define DBUF_LENGTH 1520 |
| 23 | #define PKT_MAXBUF_SIZE 1518 |
| 24 | #define PKT_MINBUF_SIZE 64 |
| 25 | #define PKT_MAXBLR_SIZE 1536 |
| 26 | #define LAST_PKTBUFSRX PKTBUFSRX - 1 |
| 27 | #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY) |
| 28 | #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST) |
| 29 | #define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF) |
| 30 | |
| 31 | /* RxBD bits definitions */ |
| 32 | #define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \ |
| 33 | BD_ENET_RX_OV | BD_ENET_RX_TR) |
| 34 | |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 35 | #include <asm/immap.h> |
| 36 | #include <asm/fsl_mcdmafec.h> |
| 37 | |
| 38 | #include "MCD_dma.h" |
| 39 | |
| 40 | DECLARE_GLOBAL_DATA_PTR; |
| 41 | |
| 42 | struct fec_info_dma fec_info[] = { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 43 | #ifdef CONFIG_SYS_FEC0_IOBASE |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 44 | { |
| 45 | 0, /* index */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 46 | CONFIG_SYS_FEC0_IOBASE, /* io base */ |
| 47 | CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */ |
| 48 | CONFIG_SYS_FEC0_MIIBASE, /* mii base */ |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 49 | -1, /* phy_addr */ |
| 50 | 0, /* duplex and speed */ |
| 51 | 0, /* phy name */ |
| 52 | 0, /* phyname init */ |
| 53 | 0, /* RX BD */ |
| 54 | 0, /* TX BD */ |
| 55 | 0, /* rx Index */ |
| 56 | 0, /* tx Index */ |
| 57 | 0, /* tx buffer */ |
| 58 | 0, /* initialized flag */ |
| 59 | (struct fec_info_dma *)-1, /* next */ |
| 60 | FEC0_RX_TASK, /* rxTask */ |
| 61 | FEC0_TX_TASK, /* txTask */ |
| 62 | FEC0_RX_PRIORITY, /* rxPri */ |
| 63 | FEC0_TX_PRIORITY, /* txPri */ |
| 64 | FEC0_RX_INIT, /* rxInit */ |
| 65 | FEC0_TX_INIT, /* txInit */ |
| 66 | 0, /* usedTbdIndex */ |
| 67 | 0, /* cleanTbdNum */ |
| 68 | }, |
| 69 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 70 | #ifdef CONFIG_SYS_FEC1_IOBASE |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 71 | { |
| 72 | 1, /* index */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 73 | CONFIG_SYS_FEC1_IOBASE, /* io base */ |
| 74 | CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */ |
| 75 | CONFIG_SYS_FEC1_MIIBASE, /* mii base */ |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 76 | -1, /* phy_addr */ |
| 77 | 0, /* duplex and speed */ |
| 78 | 0, /* phy name */ |
| 79 | 0, /* phy name init */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 80 | #ifdef CONFIG_SYS_DMA_USE_INTSRAM |
TsiChung Liew | dcb3070 | 2008-08-21 23:55:11 +0000 | [diff] [blame] | 81 | (cbd_t *)DBUF_LENGTH, /* RX BD */ |
TsiChung Liew | 1844b8f | 2008-04-30 12:11:19 -0500 | [diff] [blame] | 82 | #else |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 83 | 0, /* RX BD */ |
TsiChung Liew | 1844b8f | 2008-04-30 12:11:19 -0500 | [diff] [blame] | 84 | #endif |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 85 | 0, /* TX BD */ |
| 86 | 0, /* rx Index */ |
| 87 | 0, /* tx Index */ |
| 88 | 0, /* tx buffer */ |
| 89 | 0, /* initialized flag */ |
| 90 | (struct fec_info_dma *)-1, /* next */ |
| 91 | FEC1_RX_TASK, /* rxTask */ |
| 92 | FEC1_TX_TASK, /* txTask */ |
| 93 | FEC1_RX_PRIORITY, /* rxPri */ |
| 94 | FEC1_TX_PRIORITY, /* txPri */ |
| 95 | FEC1_RX_INIT, /* rxInit */ |
| 96 | FEC1_TX_INIT, /* txInit */ |
| 97 | 0, /* usedTbdIndex */ |
| 98 | 0, /* cleanTbdNum */ |
| 99 | } |
| 100 | #endif |
| 101 | }; |
| 102 | |
Joe Hershberger | e4e0488 | 2012-05-22 18:36:19 +0000 | [diff] [blame] | 103 | static int fec_send(struct eth_device *dev, void *packet, int length); |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 104 | static int fec_recv(struct eth_device *dev); |
| 105 | static int fec_init(struct eth_device *dev, bd_t * bd); |
| 106 | static void fec_halt(struct eth_device *dev); |
| 107 | |
| 108 | #ifdef ET_DEBUG |
| 109 | static void dbg_fec_regs(struct eth_device *dev) |
| 110 | { |
| 111 | struct fec_info_dma *info = dev->priv; |
| 112 | volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); |
| 113 | |
| 114 | printf("=====\n"); |
| 115 | printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); |
| 116 | printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr); |
| 117 | printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr); |
| 118 | printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr); |
| 119 | printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); |
| 120 | printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc); |
| 121 | printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); |
| 122 | printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr); |
| 123 | printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); |
| 124 | printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr); |
| 125 | printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur); |
| 126 | printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd); |
| 127 | printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur); |
| 128 | printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr); |
| 129 | printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur); |
| 130 | printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr); |
| 131 | printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr); |
| 132 | printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr); |
| 133 | printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr); |
| 134 | printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr); |
| 135 | printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp); |
| 136 | printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp); |
| 137 | printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar); |
| 138 | printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp); |
| 139 | printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp); |
| 140 | printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr); |
| 141 | printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr); |
| 142 | printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr); |
| 143 | printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp); |
| 144 | printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp); |
| 145 | printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar); |
| 146 | printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp); |
| 147 | printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp); |
| 148 | printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst); |
| 149 | printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr); |
| 150 | } |
| 151 | #endif |
| 152 | |
TsiChung Liew | 1844b8f | 2008-04-30 12:11:19 -0500 | [diff] [blame] | 153 | static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd, |
| 154 | int dup_spd) |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 155 | { |
| 156 | if ((dup_spd >> 16) == FULL) { |
| 157 | /* Set maximum frame length */ |
| 158 | fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | |
| 159 | FEC_RCR_PROM | 0x100; |
| 160 | fecp->tcr = FEC_TCR_FDEN; |
| 161 | } else { |
| 162 | /* Half duplex mode */ |
| 163 | fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | |
| 164 | FEC_RCR_MII_MODE | FEC_RCR_DRT; |
| 165 | fecp->tcr &= ~FEC_TCR_FDEN; |
| 166 | } |
| 167 | |
| 168 | if ((dup_spd & 0xFFFF) == _100BASET) { |
| 169 | #ifdef MII_DEBUG |
| 170 | printf("100Mbps\n"); |
| 171 | #endif |
| 172 | bd->bi_ethspeed = 100; |
| 173 | } else { |
| 174 | #ifdef MII_DEBUG |
| 175 | printf("10Mbps\n"); |
| 176 | #endif |
| 177 | bd->bi_ethspeed = 10; |
| 178 | } |
| 179 | } |
| 180 | |
Joe Hershberger | e4e0488 | 2012-05-22 18:36:19 +0000 | [diff] [blame] | 181 | static int fec_send(struct eth_device *dev, void *packet, int length) |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 182 | { |
| 183 | struct fec_info_dma *info = dev->priv; |
| 184 | cbd_t *pTbd, *pUsedTbd; |
| 185 | u16 phyStatus; |
| 186 | |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 187 | miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus); |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 188 | |
| 189 | /* process all the consumed TBDs */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 190 | while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) { |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 191 | pUsedTbd = &info->txbd[info->usedTbdIdx]; |
| 192 | if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) { |
| 193 | #ifdef ET_DEBUG |
| 194 | printf("Cannot clean TBD %d, in use\n", |
| 195 | info->cleanTbdNum); |
| 196 | #endif |
| 197 | return 0; |
| 198 | } |
| 199 | |
| 200 | /* clean this buffer descriptor */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 201 | if (info->usedTbdIdx == (CONFIG_SYS_TX_ETH_BUFFER - 1)) |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 202 | pUsedTbd->cbd_sc = BD_ENET_TX_WRAP; |
| 203 | else |
| 204 | pUsedTbd->cbd_sc = 0; |
| 205 | |
| 206 | /* update some indeces for a correct handling of the TBD ring */ |
| 207 | info->cleanTbdNum++; |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 208 | info->usedTbdIdx = (info->usedTbdIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER; |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 209 | } |
| 210 | |
| 211 | /* Check for valid length of data. */ |
| 212 | if ((length > 1500) || (length <= 0)) { |
| 213 | return -1; |
| 214 | } |
| 215 | |
| 216 | /* Check the number of vacant TxBDs. */ |
| 217 | if (info->cleanTbdNum < 1) { |
| 218 | printf("No available TxBDs ...\n"); |
| 219 | return -1; |
| 220 | } |
| 221 | |
| 222 | /* Get the first TxBD to send the mac header */ |
| 223 | pTbd = &info->txbd[info->txIdx]; |
| 224 | pTbd->cbd_datlen = length; |
| 225 | pTbd->cbd_bufaddr = (u32) packet; |
| 226 | pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY; |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 227 | info->txIdx = (info->txIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER; |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 228 | |
| 229 | /* Enable DMA transmit task */ |
| 230 | MCD_continDma(info->txTask); |
| 231 | |
| 232 | info->cleanTbdNum -= 1; |
| 233 | |
| 234 | /* wait until frame is sent . */ |
| 235 | while (pTbd->cbd_sc & BD_ENET_TX_READY) { |
| 236 | udelay(10); |
| 237 | } |
| 238 | |
| 239 | return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); |
| 240 | } |
| 241 | |
| 242 | static int fec_recv(struct eth_device *dev) |
| 243 | { |
| 244 | struct fec_info_dma *info = dev->priv; |
| 245 | volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); |
| 246 | |
| 247 | cbd_t *pRbd = &info->rxbd[info->rxIdx]; |
| 248 | u32 ievent; |
| 249 | int frame_length, len = 0; |
| 250 | |
| 251 | /* Check if any critical events have happened */ |
| 252 | ievent = fecp->eir; |
| 253 | if (ievent != 0) { |
| 254 | fecp->eir = ievent; |
| 255 | |
| 256 | if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) { |
| 257 | printf("fec_recv: error\n"); |
| 258 | fec_halt(dev); |
| 259 | fec_init(dev, NULL); |
| 260 | return 0; |
| 261 | } |
| 262 | |
| 263 | if (ievent & FEC_EIR_HBERR) { |
| 264 | /* Heartbeat error */ |
| 265 | fecp->tcr |= FEC_TCR_GTS; |
| 266 | } |
| 267 | |
| 268 | if (ievent & FEC_EIR_GRA) { |
| 269 | /* Graceful stop complete */ |
| 270 | if (fecp->tcr & FEC_TCR_GTS) { |
| 271 | printf("fec_recv: tcr_gts\n"); |
| 272 | fec_halt(dev); |
| 273 | fecp->tcr &= ~FEC_TCR_GTS; |
| 274 | fec_init(dev, NULL); |
| 275 | } |
| 276 | } |
| 277 | } |
| 278 | |
| 279 | if (!(pRbd->cbd_sc & BD_ENET_RX_EMPTY)) { |
| 280 | if ((pRbd->cbd_sc & BD_ENET_RX_LAST) |
| 281 | && !(pRbd->cbd_sc & BD_ENET_RX_ERR) |
| 282 | && ((pRbd->cbd_datlen - 4) > 14)) { |
| 283 | |
| 284 | /* Get buffer address and size */ |
| 285 | frame_length = pRbd->cbd_datlen - 4; |
| 286 | |
| 287 | /* Fill the buffer and pass it to upper layers */ |
Joe Hershberger | e4e0488 | 2012-05-22 18:36:19 +0000 | [diff] [blame] | 288 | NetReceive((uchar *)pRbd->cbd_bufaddr, frame_length); |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 289 | len = frame_length; |
| 290 | } |
| 291 | |
| 292 | /* Reset buffer descriptor as empty */ |
| 293 | if ((info->rxIdx) == (PKTBUFSRX - 1)) |
| 294 | pRbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); |
| 295 | else |
| 296 | pRbd->cbd_sc = BD_ENET_RX_EMPTY; |
| 297 | |
| 298 | pRbd->cbd_datlen = PKTSIZE_ALIGN; |
| 299 | |
| 300 | /* Now, we have an empty RxBD, restart the DMA receive task */ |
| 301 | MCD_continDma(info->rxTask); |
| 302 | |
| 303 | /* Increment BD count */ |
| 304 | info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX; |
| 305 | } |
| 306 | |
| 307 | return len; |
| 308 | } |
| 309 | |
| 310 | static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac) |
| 311 | { |
| 312 | u8 currByte; /* byte for which to compute the CRC */ |
| 313 | int byte; /* loop - counter */ |
| 314 | int bit; /* loop - counter */ |
| 315 | u32 crc = 0xffffffff; /* initial value */ |
| 316 | |
| 317 | for (byte = 0; byte < 6; byte++) { |
| 318 | currByte = mac[byte]; |
| 319 | for (bit = 0; bit < 8; bit++) { |
| 320 | if ((currByte & 0x01) ^ (crc & 0x01)) { |
| 321 | crc >>= 1; |
| 322 | crc = crc ^ 0xedb88320; |
| 323 | } else { |
| 324 | crc >>= 1; |
| 325 | } |
| 326 | currByte >>= 1; |
| 327 | } |
| 328 | } |
| 329 | |
| 330 | crc = crc >> 26; |
| 331 | |
| 332 | /* Set individual hash table register */ |
| 333 | if (crc >= 32) { |
| 334 | fecp->ialr = (1 << (crc - 32)); |
| 335 | fecp->iaur = 0; |
| 336 | } else { |
| 337 | fecp->ialr = 0; |
| 338 | fecp->iaur = (1 << crc); |
| 339 | } |
| 340 | |
| 341 | /* Set physical address */ |
| 342 | fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3]; |
| 343 | fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808; |
| 344 | |
| 345 | /* Clear multicast address hash table */ |
| 346 | fecp->gaur = 0; |
| 347 | fecp->galr = 0; |
| 348 | } |
| 349 | |
| 350 | static int fec_init(struct eth_device *dev, bd_t * bd) |
| 351 | { |
| 352 | struct fec_info_dma *info = dev->priv; |
| 353 | volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); |
| 354 | int i; |
Mike Frysinger | b203965 | 2009-02-11 19:01:26 -0500 | [diff] [blame] | 355 | uchar enetaddr[6]; |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 356 | |
| 357 | #ifdef ET_DEBUG |
| 358 | printf("fec_init: iobase 0x%08x ...\n", info->iobase); |
| 359 | #endif |
| 360 | |
| 361 | fecpin_setclear(dev, 1); |
| 362 | |
| 363 | fec_halt(dev); |
| 364 | |
| 365 | #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 366 | defined (CONFIG_SYS_DISCOVER_PHY) |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 367 | |
| 368 | mii_init(); |
| 369 | |
| 370 | set_fec_duplex_speed(fecp, bd, info->dup_spd); |
| 371 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 372 | #ifndef CONFIG_SYS_DISCOVER_PHY |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 373 | set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 374 | #endif /* ifndef CONFIG_SYS_DISCOVER_PHY */ |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 375 | #endif /* CONFIG_CMD_MII || CONFIG_MII */ |
| 376 | |
| 377 | /* We use strictly polling mode only */ |
| 378 | fecp->eimr = 0; |
| 379 | |
| 380 | /* Clear any pending interrupt */ |
| 381 | fecp->eir = 0xffffffff; |
| 382 | |
| 383 | /* Set station address */ |
Mike Frysinger | b203965 | 2009-02-11 19:01:26 -0500 | [diff] [blame] | 384 | if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) |
| 385 | eth_getenv_enetaddr("ethaddr", enetaddr); |
| 386 | else |
| 387 | eth_getenv_enetaddr("eth1addr", enetaddr); |
| 388 | fec_set_hwaddr(fecp, enetaddr); |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 389 | |
| 390 | /* Set Opcode/Pause Duration Register */ |
| 391 | fecp->opd = 0x00010020; |
| 392 | |
| 393 | /* Setup Buffers and Buffer Desriptors */ |
| 394 | info->rxIdx = 0; |
| 395 | info->txIdx = 0; |
| 396 | |
| 397 | /* Setup Receiver Buffer Descriptors (13.14.24.18) |
| 398 | * Settings: Empty, Wrap */ |
| 399 | for (i = 0; i < PKTBUFSRX; i++) { |
| 400 | info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; |
| 401 | info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN; |
| 402 | info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; |
| 403 | } |
| 404 | info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; |
| 405 | |
| 406 | /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) |
| 407 | * Settings: Last, Tx CRC */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 408 | for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) { |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 409 | info->txbd[i].cbd_sc = 0; |
| 410 | info->txbd[i].cbd_datlen = 0; |
| 411 | info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); |
| 412 | } |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 413 | info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP; |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 414 | |
| 415 | info->usedTbdIdx = 0; |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 416 | info->cleanTbdNum = CONFIG_SYS_TX_ETH_BUFFER; |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 417 | |
| 418 | /* Set Rx FIFO alarm and granularity value */ |
| 419 | fecp->rfcr = 0x0c000000; |
| 420 | fecp->rfar = 0x0000030c; |
| 421 | |
| 422 | /* Set Tx FIFO granularity value */ |
| 423 | fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000; |
| 424 | fecp->tfar = 0x00000080; |
| 425 | |
| 426 | fecp->tfwr = 0x2; |
| 427 | fecp->ctcwr = 0x03000000; |
| 428 | |
| 429 | /* Enable DMA receive task */ |
| 430 | MCD_startDma(info->rxTask, /* Dma channel */ |
| 431 | (s8 *) info->rxbd, /*Source Address */ |
| 432 | 0, /* Source increment */ |
| 433 | (s8 *) (&fecp->rfdr), /* dest */ |
| 434 | 4, /* dest increment */ |
| 435 | 0, /* DMA size */ |
| 436 | 4, /* xfer size */ |
| 437 | info->rxInit, /* initiator */ |
| 438 | info->rxPri, /* priority */ |
| 439 | (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF), /* Flags */ |
| 440 | (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */ |
| 441 | ); |
| 442 | |
| 443 | /* Enable DMA tx task with no ready buffer descriptors */ |
| 444 | MCD_startDma(info->txTask, /* Dma channel */ |
| 445 | (s8 *) info->txbd, /*Source Address */ |
| 446 | 0, /* Source increment */ |
| 447 | (s8 *) (&fecp->tfdr), /* dest */ |
| 448 | 4, /* dest incr */ |
| 449 | 0, /* DMA size */ |
| 450 | 4, /* xfer size */ |
| 451 | info->txInit, /* initiator */ |
| 452 | info->txPri, /* priority */ |
| 453 | (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF), /* Flags */ |
| 454 | (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */ |
| 455 | ); |
| 456 | |
| 457 | /* Now enable the transmit and receive processing */ |
| 458 | fecp->ecr |= FEC_ECR_ETHER_EN; |
| 459 | |
| 460 | return 1; |
| 461 | } |
| 462 | |
| 463 | static void fec_halt(struct eth_device *dev) |
| 464 | { |
| 465 | struct fec_info_dma *info = dev->priv; |
| 466 | volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); |
| 467 | int counter = 0xffff; |
| 468 | |
| 469 | /* issue graceful stop command to the FEC transmitter if necessary */ |
| 470 | fecp->tcr |= FEC_TCR_GTS; |
| 471 | |
| 472 | /* wait for graceful stop to register */ |
| 473 | while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ; |
| 474 | |
| 475 | /* Disable DMA tasks */ |
| 476 | MCD_killDma(info->txTask); |
| 477 | MCD_killDma(info->rxTask);; |
| 478 | |
| 479 | /* Disable the Ethernet Controller */ |
| 480 | fecp->ecr &= ~FEC_ECR_ETHER_EN; |
| 481 | |
| 482 | /* Clear FIFO status registers */ |
| 483 | fecp->rfsr &= FIFO_ERRSTAT; |
| 484 | fecp->tfsr &= FIFO_ERRSTAT; |
| 485 | |
| 486 | fecp->frst = 0x01000000; |
| 487 | |
| 488 | /* Issue a reset command to the FEC chip */ |
| 489 | fecp->ecr |= FEC_ECR_RESET; |
| 490 | |
| 491 | /* wait at least 20 clock cycles */ |
| 492 | udelay(10000); |
| 493 | |
| 494 | #ifdef ET_DEBUG |
| 495 | printf("Ethernet task stopped\n"); |
| 496 | #endif |
| 497 | } |
| 498 | |
| 499 | int mcdmafec_initialize(bd_t * bis) |
| 500 | { |
| 501 | struct eth_device *dev; |
| 502 | int i; |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 503 | #ifdef CONFIG_SYS_DMA_USE_INTSRAM |
| 504 | u32 tmp = CONFIG_SYS_INTSRAM + 0x2000; |
TsiChung Liew | 1844b8f | 2008-04-30 12:11:19 -0500 | [diff] [blame] | 505 | #endif |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 506 | |
| 507 | for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { |
| 508 | |
| 509 | dev = |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 510 | (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE, |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 511 | sizeof *dev); |
| 512 | if (dev == NULL) |
| 513 | hang(); |
| 514 | |
| 515 | memset(dev, 0, sizeof(*dev)); |
| 516 | |
| 517 | sprintf(dev->name, "FEC%d", fec_info[i].index); |
| 518 | |
| 519 | dev->priv = &fec_info[i]; |
| 520 | dev->init = fec_init; |
| 521 | dev->halt = fec_halt; |
| 522 | dev->send = fec_send; |
| 523 | dev->recv = fec_recv; |
| 524 | |
| 525 | /* setup Receive and Transmit buffer descriptor */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 526 | #ifdef CONFIG_SYS_DMA_USE_INTSRAM |
TsiChung Liew | dcb3070 | 2008-08-21 23:55:11 +0000 | [diff] [blame] | 527 | fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp); |
| 528 | tmp = (u32)fec_info[i].rxbd; |
TsiChung Liew | 1844b8f | 2008-04-30 12:11:19 -0500 | [diff] [blame] | 529 | fec_info[i].txbd = |
TsiChung Liew | dcb3070 | 2008-08-21 23:55:11 +0000 | [diff] [blame] | 530 | (cbd_t *)((u32)fec_info[i].txbd + tmp + |
| 531 | (PKTBUFSRX * sizeof(cbd_t))); |
| 532 | tmp = (u32)fec_info[i].txbd; |
TsiChung Liew | 1844b8f | 2008-04-30 12:11:19 -0500 | [diff] [blame] | 533 | fec_info[i].txbuf = |
TsiChung Liew | dcb3070 | 2008-08-21 23:55:11 +0000 | [diff] [blame] | 534 | (char *)((u32)fec_info[i].txbuf + tmp + |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 535 | (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); |
TsiChung Liew | dcb3070 | 2008-08-21 23:55:11 +0000 | [diff] [blame] | 536 | tmp = (u32)fec_info[i].txbuf; |
TsiChung Liew | 1844b8f | 2008-04-30 12:11:19 -0500 | [diff] [blame] | 537 | #else |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 538 | fec_info[i].rxbd = |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 539 | (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 540 | (PKTBUFSRX * sizeof(cbd_t))); |
| 541 | fec_info[i].txbd = |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 542 | (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, |
| 543 | (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 544 | fec_info[i].txbuf = |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 545 | (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); |
TsiChung Liew | 1844b8f | 2008-04-30 12:11:19 -0500 | [diff] [blame] | 546 | #endif |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 547 | |
| 548 | #ifdef ET_DEBUG |
| 549 | printf("rxbd %x txbd %x\n", |
| 550 | (int)fec_info[i].rxbd, (int)fec_info[i].txbd); |
| 551 | #endif |
| 552 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 553 | fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32); |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 554 | |
| 555 | eth_register(dev); |
| 556 | |
| 557 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
| 558 | miiphy_register(dev->name, |
| 559 | mcffec_miiphy_read, mcffec_miiphy_write); |
| 560 | #endif |
| 561 | |
| 562 | if (i > 0) |
| 563 | fec_info[i - 1].next = &fec_info[i]; |
| 564 | } |
| 565 | fec_info[i - 1].next = &fec_info[0]; |
| 566 | |
| 567 | /* default speed */ |
| 568 | bis->bi_ethspeed = 10; |
| 569 | |
Ben Warren | e7edd4e | 2008-08-26 22:12:36 -0700 | [diff] [blame] | 570 | return 0; |
TsiChungLiew | 95e8787 | 2008-01-15 14:00:25 -0600 | [diff] [blame] | 571 | } |