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git01.mediatek.com / filogic / uboot / 5ace29c4751f83bfca95f5b14d9e5bd563e0d108 / . / board / nvidia / dts / tegra30-cardhu.dts
blob: 4d22b48ee917036f3da1e64e78a13e19294392d0 [file] [log] [blame]
Tom Warrenaa35e1e2012-12-11 13:34:16 +0000[diff] [blame]1/dts-v1/;
2
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]3#include "tegra30.dtsi"
Tom Warrenaa35e1e2012-12-11 13:34:16 +0000[diff] [blame]4
5/ {
6 model = "NVIDIA Cardhu";
7 compatible = "nvidia,cardhu", "nvidia,tegra30";
8
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]9 aliases {
10 i2c0 = "/i2c@7000d000";
11 i2c1 = "/i2c@7000c000";
12 i2c2 = "/i2c@7000c400";
13 i2c3 = "/i2c@7000c500";
14 i2c4 = "/i2c@7000c700";
Tom Warren20515be2013-02-26 11:14:17 -0700[diff] [blame]15 sdhci0 = "/sdhci@78000600";
16 sdhci1 = "/sdhci@78000000";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]17 };
18
Tom Warrenaa35e1e2012-12-11 13:34:16 +0000[diff] [blame]19 memory {
20 device_type = "memory";
21 reg = <0x80000000 0x40000000>;
22 };
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]23
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]24 i2c@7000c000 {
Tom Warrene8cf3dd2013-02-21 13:33:23 +0000[diff] [blame]25 status = "okay";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]26 clock-frequency = <100000>;
27 };
28
29 i2c@7000c400 {
Tom Warrene8cf3dd2013-02-21 13:33:23 +0000[diff] [blame]30 status = "okay";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]31 clock-frequency = <100000>;
32 };
33
34 i2c@7000c500 {
Tom Warrene8cf3dd2013-02-21 13:33:23 +0000[diff] [blame]35 status = "okay";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]36 clock-frequency = <100000>;
37 };
38
39 i2c@7000c700 {
Tom Warrene8cf3dd2013-02-21 13:33:23 +0000[diff] [blame]40 status = "okay";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]41 clock-frequency = <100000>;
42 };
43
44 i2c@7000d000 {
Tom Warrene8cf3dd2013-02-21 13:33:23 +0000[diff] [blame]45 status = "okay";
Tom Warren392715b2012-12-21 15:59:15 -0700[diff] [blame]46 clock-frequency = <100000>;
47 };
Allen Martin43b04292013-01-29 13:51:26 +0000[diff] [blame]48
49 spi@7000da00 {
50 status = "okay";
51 spi-max-frequency = <25000000>;
52 };
Tom Warren20515be2013-02-26 11:14:17 -0700[diff] [blame]53
54 sdhci@78000000 {
55 status = "okay";
56 cd-gpios = <&gpio 69 1>; /* gpio PI5 */
57 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
58 power-gpios = <&gpio 31 0>; /* gpio PD7 */
59 bus-width = <4>;
60 };
61
62 sdhci@78000600 {
63 status = "okay";
64 bus-width = <8>;
65 };
Tom Warrenaa35e1e2012-12-11 13:34:16 +0000[diff] [blame]66};