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Stelian Pop69c925f2008-05-08 18:52:23 +02001/*
2 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Stelian Pop69c925f2008-05-08 18:52:23 +02004 * Lead Tech Design <www.leadtechdesign.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
Stelian Pope068a9b2008-05-08 14:52:31 +020026#include <asm/sizes.h>
Stelian Pop69c925f2008-05-08 18:52:23 +020027#include <asm/arch/at91sam9263.h>
Stelian Pop69c925f2008-05-08 18:52:23 +020028#include <asm/arch/at91sam9_smc.h>
Jean-Christophe PLAGNIOL-VILLARD6b0b3db2009-03-21 21:07:59 +010029#include <asm/arch/at91_common.h>
Stelian Pop69c925f2008-05-08 18:52:23 +020030#include <asm/arch/at91_pmc.h>
31#include <asm/arch/at91_rstc.h>
Jens Scharsigc3c10ea2010-02-03 22:47:18 +010032#include <asm/arch/at91_matrix.h>
33#include <asm/arch/at91_pio.h>
Jean-Christophe PLAGNIOL-VILLARD23164f12009-04-16 21:30:44 +020034#include <asm/arch/clk.h>
Xu, Hong504e4e12011-06-10 21:31:26 +000035#include <asm/io.h>
36#include <asm/arch/gpio.h>
Ben Warren057d2022008-08-12 22:11:53 -070037#include <asm/arch/hardware.h>
Stelian Pope068a9b2008-05-08 14:52:31 +020038#include <lcd.h>
39#include <atmel_lcdc.h>
Stelian Pop69c925f2008-05-08 18:52:23 +020040#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
41#include <net.h>
42#endif
Ben Warren057d2022008-08-12 22:11:53 -070043#include <netdev.h>
Stelian Pop69c925f2008-05-08 18:52:23 +020044
45DECLARE_GLOBAL_DATA_PTR;
46
47/* ------------------------------------------------------------------------- */
48/*
49 * Miscelaneous platform dependent initialisations
50 */
51
Stelian Pop69c925f2008-05-08 18:52:23 +020052#ifdef CONFIG_CMD_NAND
53static void at91sam9263ek_nand_hw_init(void)
54{
55 unsigned long csa;
Xu, Hong504e4e12011-06-10 21:31:26 +000056 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
57 at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
58 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
Stelian Pop69c925f2008-05-08 18:52:23 +020059
60 /* Enable CS3 */
Jens Scharsigc3c10ea2010-02-03 22:47:18 +010061 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
62 writel(csa, &matrix->csa[0]);
63
64 /* Enable CS3 */
Stelian Pop69c925f2008-05-08 18:52:23 +020065
66 /* Configure SMC CS3 for NAND/SmartMedia */
Jens Scharsigc3c10ea2010-02-03 22:47:18 +010067 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
68 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
69 &smc->cs[3].setup);
70
71 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
72 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
73 &smc->cs[3].pulse);
74
75 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
76 &smc->cs[3].cycle);
77 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
78 AT91_SMC_MODE_EXNW_DISABLE |
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020079#ifdef CONFIG_SYS_NAND_DBW_16
Jens Scharsigc3c10ea2010-02-03 22:47:18 +010080 AT91_SMC_MODE_DBW_16 |
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020081#else /* CONFIG_SYS_NAND_DBW_8 */
Jens Scharsigc3c10ea2010-02-03 22:47:18 +010082 AT91_SMC_MODE_DBW_8 |
Stelian Pop69c925f2008-05-08 18:52:23 +020083#endif
Jens Scharsigc3c10ea2010-02-03 22:47:18 +010084 AT91_SMC_MODE_TDF_CYCLE(2),
85 &smc->cs[3].mode);
Stelian Pop69c925f2008-05-08 18:52:23 +020086
Xu, Hong504e4e12011-06-10 21:31:26 +000087 writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE,
Jens Scharsigc3c10ea2010-02-03 22:47:18 +010088 &pmc->pcer);
Stelian Pop69c925f2008-05-08 18:52:23 +020089
90 /* Configure RDY/BSY */
Xu, Hong504e4e12011-06-10 21:31:26 +000091 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
Stelian Pop69c925f2008-05-08 18:52:23 +020092
93 /* Enable NandFlash */
Xu, Hong504e4e12011-06-10 21:31:26 +000094 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
Stelian Pop69c925f2008-05-08 18:52:23 +020095}
96#endif
97
Stelian Pop69c925f2008-05-08 18:52:23 +020098#ifdef CONFIG_MACB
99static void at91sam9263ek_macb_hw_init(void)
100{
Jens Scharsigc3c10ea2010-02-03 22:47:18 +0100101 unsigned long erstl;
Xu, Hong504e4e12011-06-10 21:31:26 +0000102 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
103 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
104 at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
Stelian Pop69c925f2008-05-08 18:52:23 +0200105 /* Enable clock */
Xu, Hong504e4e12011-06-10 21:31:26 +0000106 writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
Stelian Pop69c925f2008-05-08 18:52:23 +0200107
108 /*
109 * Disable pull-up on:
110 * RXDV (PC25) => PHY normal mode (not Test mode)
111 * ERX0 (PE25) => PHY ADDR0
112 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
113 *
114 * PHY has internal pull-down
115 */
Stelian Pop69c925f2008-05-08 18:52:23 +0200116
Jens Scharsigc3c10ea2010-02-03 22:47:18 +0100117 writel(1 << 25, &pio->pioc.pudr);
118 writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
Sedji Gaouaou419a5812009-06-24 08:32:09 +0200119
Jens Scharsigc3c10ea2010-02-03 22:47:18 +0100120 erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
Stelian Pop69c925f2008-05-08 18:52:23 +0200121
Jens Scharsigc3c10ea2010-02-03 22:47:18 +0100122 /* Need to reset PHY -> 500ms reset */
123 writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
124 AT91_RSTC_MR_URSTEN, &rstc->mr);
Stelian Pop69c925f2008-05-08 18:52:23 +0200125
Jens Scharsigc3c10ea2010-02-03 22:47:18 +0100126 writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
Stelian Pop69c925f2008-05-08 18:52:23 +0200127 /* Wait for end hardware reset */
Jens Scharsigc3c10ea2010-02-03 22:47:18 +0100128 while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
129 ;
Stelian Pop69c925f2008-05-08 18:52:23 +0200130
Stelian Popefff2672008-05-22 00:15:40 +0200131 /* Restore NRST value */
Jens Scharsigc3c10ea2010-02-03 22:47:18 +0100132 writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
Stelian Popefff2672008-05-22 00:15:40 +0200133
Stelian Pop69c925f2008-05-08 18:52:23 +0200134 /* Re-enable pull-up */
Jens Scharsigc3c10ea2010-02-03 22:47:18 +0100135 writel(1 << 25, &pio->pioc.puer);
136 writel((1 << 25) | (1 <<26), &pio->pioe.puer);
Stelian Pop69c925f2008-05-08 18:52:23 +0200137
Jean-Christophe PLAGNIOL-VILLARDfafa9232009-03-21 21:08:00 +0100138 at91_macb_hw_init();
Stelian Pop69c925f2008-05-08 18:52:23 +0200139}
140#endif
141
Stelian Pope068a9b2008-05-08 14:52:31 +0200142#ifdef CONFIG_LCD
143vidinfo_t panel_info = {
144 vl_col: 240,
145 vl_row: 320,
146 vl_clk: 4965000,
147 vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
148 ATMEL_LCDC_INVFRAME_INVERTED,
149 vl_bpix: 3,
150 vl_tft: 1,
151 vl_hsync_len: 5,
152 vl_left_margin: 1,
153 vl_right_margin:33,
154 vl_vsync_len: 1,
155 vl_upper_margin:1,
156 vl_lower_margin:0,
Xu, Hong504e4e12011-06-10 21:31:26 +0000157 mmio: ATMEL_BASE_LCDC,
Stelian Pope068a9b2008-05-08 14:52:31 +0200158};
159
160void lcd_enable(void)
161{
Jens Scharsigc3c10ea2010-02-03 22:47:18 +0100162 at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power up */
Stelian Pope068a9b2008-05-08 14:52:31 +0200163}
164
165void lcd_disable(void)
166{
Jens Scharsigc3c10ea2010-02-03 22:47:18 +0100167 at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power down */
Stelian Pope068a9b2008-05-08 14:52:31 +0200168}
169
170static void at91sam9263ek_lcd_hw_init(void)
171{
Xu, Hong504e4e12011-06-10 21:31:26 +0000172 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
Stelian Pope068a9b2008-05-08 14:52:31 +0200173
Jens Scharsigc3c10ea2010-02-03 22:47:18 +0100174 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
175 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
176 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
177 at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
178 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
179 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
180 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
181 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
182 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
183 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
184 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
185 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
186 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
187 at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
188 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
189 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
190 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
191 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
192 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
193 at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
194 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
195 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
Stelian Pope068a9b2008-05-08 14:52:31 +0200196
Xu, Hong504e4e12011-06-10 21:31:26 +0000197 writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
198 gd->fb_base = ATMEL_BASE_SRAM0;
Stelian Pope068a9b2008-05-08 14:52:31 +0200199}
Haavard Skinnemoenddbcf952008-09-01 16:21:22 +0200200
201#ifdef CONFIG_LCD_INFO
202#include <nand.h>
203#include <version.h>
204
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +0200205#ifndef CONFIG_SYS_NO_FLASH
206extern flash_info_t flash_info[];
207#endif
208
Haavard Skinnemoenddbcf952008-09-01 16:21:22 +0200209void lcd_show_board_info(void)
210{
211 ulong dram_size, nand_size;
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +0200212#ifndef CONFIG_SYS_NO_FLASH
213 ulong flash_size;
214#endif
Haavard Skinnemoenddbcf952008-09-01 16:21:22 +0200215 int i;
216 char temp[32];
217
218 lcd_printf ("%s\n", U_BOOT_VERSION);
219 lcd_printf ("(C) 2008 ATMEL Corp\n");
220 lcd_printf ("at91support@atmel.com\n");
221 lcd_printf ("%s CPU at %s MHz\n",
Xu, Hong504e4e12011-06-10 21:31:26 +0000222 ATMEL_CPU_NAME,
Jean-Christophe PLAGNIOL-VILLARD23164f12009-04-16 21:30:44 +0200223 strmhz(temp, get_cpu_clk_rate()));
Haavard Skinnemoenddbcf952008-09-01 16:21:22 +0200224
225 dram_size = 0;
226 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
227 dram_size += gd->bd->bi_dram[i].size;
228 nand_size = 0;
229 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
230 nand_size += nand_info[i].size;
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +0200231#ifndef CONFIG_SYS_NO_FLASH
232 flash_size = 0;
233 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
234 flash_size += flash_info[i].size;
235#endif
236 lcd_printf (" %ld MB SDRAM, %ld MB NAND",
Haavard Skinnemoenddbcf952008-09-01 16:21:22 +0200237 dram_size >> 20,
238 nand_size >> 20 );
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +0200239#ifndef CONFIG_SYS_NO_FLASH
240 lcd_printf (",\n %ld MB NOR",
241 flash_size >> 20);
242#endif
243 lcd_puts ("\n");
Haavard Skinnemoenddbcf952008-09-01 16:21:22 +0200244}
245#endif /* CONFIG_LCD_INFO */
Stelian Pope068a9b2008-05-08 14:52:31 +0200246#endif
247
Xu, Hong504e4e12011-06-10 21:31:26 +0000248int board_early_init_f(void)
249{
250 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
251
252 /* Enable clocks for all PIOs */
253 writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
254 (1 << ATMEL_ID_PIOCDE),
255 &pmc->pcer);
256
esw@bus-elektronik.de470af012012-03-19 04:25:59 +0000257 at91_seriald_hw_init();
Xu, Hong504e4e12011-06-10 21:31:26 +0000258 return 0;
259}
260
Stelian Pop69c925f2008-05-08 18:52:23 +0200261int board_init(void)
262{
Stelian Pop69c925f2008-05-08 18:52:23 +0200263 /* arch number of AT91SAM9263EK-Board */
264 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
265 /* adress of boot parameters */
Xu, Hong504e4e12011-06-10 21:31:26 +0000266 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
Stelian Pop69c925f2008-05-08 18:52:23 +0200267
Stelian Pop69c925f2008-05-08 18:52:23 +0200268#ifdef CONFIG_CMD_NAND
269 at91sam9263ek_nand_hw_init();
270#endif
271#ifdef CONFIG_HAS_DATAFLASH
Jens Scharsigc3c10ea2010-02-03 22:47:18 +0100272 at91_set_pio_output(AT91_PIO_PORTE, 20, 1); /* select spi0 clock */
Jean-Christophe PLAGNIOL-VILLARD12dcdef2009-03-21 21:07:59 +0100273 at91_spi0_hw_init(1 << 0);
Stelian Pop69c925f2008-05-08 18:52:23 +0200274#endif
275#ifdef CONFIG_MACB
276 at91sam9263ek_macb_hw_init();
277#endif
278#ifdef CONFIG_USB_OHCI_NEW
Jean-Christophe PLAGNIOL-VILLARD4fc81fb2009-03-21 21:08:00 +0100279 at91_uhp_hw_init();
Stelian Pop69c925f2008-05-08 18:52:23 +0200280#endif
Stelian Pope068a9b2008-05-08 14:52:31 +0200281#ifdef CONFIG_LCD
282 at91sam9263ek_lcd_hw_init();
283#endif
Stelian Pop69c925f2008-05-08 18:52:23 +0200284 return 0;
285}
286
287int dram_init(void)
288{
Xu, Hong504e4e12011-06-10 21:31:26 +0000289 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
290 CONFIG_SYS_SDRAM_SIZE);
291
Stelian Pop69c925f2008-05-08 18:52:23 +0200292 return 0;
293}
294
295#ifdef CONFIG_RESET_PHY_R
296void reset_phy(void)
297{
Stelian Pop69c925f2008-05-08 18:52:23 +0200298}
299#endif
Ben Warren057d2022008-08-12 22:11:53 -0700300
301int board_eth_init(bd_t *bis)
302{
303 int rc = 0;
304#ifdef CONFIG_MACB
Xu, Hong504e4e12011-06-10 21:31:26 +0000305 rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x00);
Ben Warren057d2022008-08-12 22:11:53 -0700306#endif
307 return rc;
308}