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git01.mediatek.com / filogic / uboot / 5ace29c4751f83bfca95f5b14d9e5bd563e0d108 / . / arch / powerpc / include / asm / fsl_dtsec.h
blob: d1d993c5ac0f541735e841ab1573efd008bd73ed [file] [log] [blame]
Kumar Gala2683c532011-04-13 08:37:44 -0500[diff] [blame]1/*
2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 */
19
20#ifndef __DTSEC_H__
21#define __DTSEC_H__
22
23#include <asm/types.h>
24
25struct dtsec {
26 u32 tsec_id; /* controller ID and version */
27 u32 tsec_id2; /* controller ID and configuration */
28 u32 ievent; /* interrupt event */
29 u32 imask; /* interrupt mask */
30 u32 res0;
31 u32 ecntrl; /* ethernet control and configuration */
32 u32 ptv; /* pause time value */
33 u32 tbipa; /* TBI PHY address */
34 u32 res1[8];
35 u32 tctrl; /* Transmit control register */
36 u32 res2[3];
37 u32 rctrl; /* Receive control register */
38 u32 res3[11];
39 u32 igaddr[8]; /* Individual group address */
40 u32 gaddr[8]; /* group address */
41 u32 res4[16];
42 u32 maccfg1; /* MAC configuration register 1 */
43 u32 maccfg2; /* MAC configuration register 2 */
44 u32 ipgifg; /* inter-packet/inter-frame gap */
45 u32 hafdup; /* half-duplex control */
46 u32 maxfrm; /* Maximum frame size */
47 u32 res5[3];
48 u32 miimcfg; /* MII management configuration */
49 u32 miimcom; /* MII management command */
50 u32 miimadd; /* MII management address */
51 u32 miimcon; /* MII management control */
52 u32 miimstat; /* MII management status */
53 u32 miimind; /* MII management indicator */
54 u32 res6;
55 u32 ifstat; /* Interface status */
56 u32 macstnaddr1; /* MAC station address 1 */
57 u32 macstnaddr2; /* MAC station address 2 */
58 u32 res7[46];
59 /* transmit and receive counter */
60 u32 tr64; /* Tx and Rx 64 bytes frame */
61 u32 tr127; /* Tx and Rx 65 to 127 bytes frame */
62 u32 tr255; /* Tx and Rx 128 to 255 bytes frame */
63 u32 tr511; /* Tx and Rx 256 to 511 bytes frame */
64 u32 tr1k; /* Tx and Rx 512 to 1023 bytes frame */
65 u32 trmax; /* Tx and Rx 1024 to 1518 bytes frame */
66 u32 trmgv; /* Tx and Rx 1519 to 1522 good VLAN frame */
67 /* receive counters */
68 u32 rbyt; /* Receive byte counter */
69 u32 rpkt; /* Receive packet counter */
70 u32 rfcs; /* Receive FCS error */
71 u32 rmca; /* Receive multicast packet */
72 u32 rbca; /* Receive broadcast packet */
73 u32 rxcf; /* Receive control frame */
74 u32 rxpf; /* Receive pause frame */
75 u32 rxuo; /* Receive unknown OP code */
76 u32 raln; /* Receive alignment error */
77 u32 rflr; /* Receive frame length error */
78 u32 rcde; /* Receive code error */
79 u32 rcse; /* Receive carrier sense error */
80 u32 rund; /* Receive undersize packet */
81 u32 rovr; /* Receive oversize packet */
82 u32 rfrg; /* Receive fragments counter */
83 u32 rjbr; /* Receive jabber counter */
84 u32 rdrp; /* Receive drop counter */
85 /* transmit counters */
86 u32 tbyt; /* Transmit byte counter */
87 u32 tpkt; /* Transmit packet */
88 u32 tmca; /* Transmit multicast packet */
89 u32 tbca; /* Transmit broadcast packet */
90 u32 txpf; /* Transmit pause control frame */
91 u32 tdfr; /* Transmit deferral packet */
92 u32 tedf; /* Transmit excessive deferral pkt */
93 u32 tscl; /* Transmit single collision pkt */
94 u32 tmcl; /* Transmit multiple collision pkt */
95 u32 tlcl; /* Transmit late collision pkt */
96 u32 txcl; /* Transmit excessive collision */
97 u32 tncl; /* Transmit total collision */
98 u32 res8;
99 u32 tdrp; /* Transmit drop frame */
100 u32 tjbr; /* Transmit jabber frame */
101 u32 tfcs; /* Transmit FCS error */
102 u32 txcf; /* Transmit control frame */
103 u32 tovr; /* Transmit oversize frame */
104 u32 tund; /* Transmit undersize frame */
105 u32 tfrg; /* Transmit fragments frame */
106 /* counter controls */
107 u32 car1; /* carry register 1 */
108 u32 car2; /* carry register 2 */
109 u32 cam1; /* carry register 1 mask */
110 u32 cam2; /* carry register 2 mask */
111 u32 res9[80];
112};
113
114
115/* TBI register addresses */
116#define TBI_CR 0x00
117#define TBI_SR 0x01
118#define TBI_ANA 0x04
119#define TBI_ANLPBPA 0x05
120#define TBI_ANEX 0x06
121#define TBI_TBICON 0x11
122
123/* TBI MDIO register bit fields*/
124#define TBICON_CLK_SELECT 0x0020
125#define TBIANA_ASYMMETRIC_PAUSE 0x0100
126#define TBIANA_SYMMETRIC_PAUSE 0x0080
127#define TBIANA_HALF_DUPLEX 0x0040
128#define TBIANA_FULL_DUPLEX 0x0020
129#define TBICR_PHY_RESET 0x8000
130#define TBICR_ANEG_ENABLE 0x1000
131#define TBICR_RESTART_ANEG 0x0200
132#define TBICR_FULL_DUPLEX 0x0100
133#define TBICR_SPEED1_SET 0x0040
134
135/* IEVENT - interrupt events register */
136#define IEVENT_BABR 0x80000000 /* Babbling receive error */
137#define IEVENT_RXC 0x40000000 /* pause control frame received */
138#define IEVENT_MSRO 0x04000000 /* MIB counter overflow */
139#define IEVENT_GTSC 0x02000000 /* Graceful transmit stop complete */
140#define IEVENT_BABT 0x01000000 /* Babbling transmit error */
141#define IEVENT_TXC 0x00800000 /* control frame transmitted */
142#define IEVENT_TXE 0x00400000 /* Transmit channel error */
143#define IEVENT_LC 0x00040000 /* Late collision occurred */
144#define IEVENT_CRL 0x00020000 /* Collision retry exceed limit */
145#define IEVENT_XFUN 0x00010000 /* Transmit FIFO underrun */
146#define IEVENT_ABRT 0x00008000 /* Transmit packet abort */
147#define IEVENT_MMRD 0x00000400 /* MII management read complete */
148#define IEVENT_MMWR 0x00000200 /* MII management write complete */
149#define IEVENT_GRSC 0x00000100 /* Graceful stop complete */
150#define IEVENT_TDPE 0x00000002 /* Internal data parity error on Tx */
151#define IEVENT_RDPE 0x00000001 /* Internal data parity error on Rx */
152
153#define IEVENT_CLEAR_ALL 0xffffffff
154
155/* IMASK - interrupt mask register */
156#define IMASK_BREN 0x80000000 /* Babbling receive enable */
157#define IMASK_RXCEN 0x40000000 /* receive control enable */
158#define IMASK_MSROEN 0x04000000 /* MIB counter overflow enable */
159#define IMASK_GTSCEN 0x02000000 /* Graceful Tx stop complete enable */
160#define IMASK_BTEN 0x01000000 /* Babbling transmit error enable */
161#define IMASK_TXCEN 0x00800000 /* control frame transmitted enable */
162#define IMASK_TXEEN 0x00400000 /* Transmit channel error enable */
163#define IMASK_LCEN 0x00040000 /* Late collision interrupt enable */
164#define IMASK_CRLEN 0x00020000 /* Collision retry exceed limit */
165#define IMASK_XFUNEN 0x00010000 /* Transmit FIFO underrun enable */
166#define IMASK_ABRTEN 0x00008000 /* Transmit packet abort enable */
167#define IMASK_MMRDEN 0x00000400 /* MII management read complete enable */
168#define IMASK_MMWREN 0x00000200 /* MII management write complete enable */
169#define IMASK_GRSCEN 0x00000100 /* Graceful stop complete interrupt enable */
170#define IMASK_TDPEEN 0x00000002 /* Internal data parity error on Tx enable */
171#define IMASK_RDPEEN 0x00000001 /* Internal data parity error on Rx enable */
172
173#define IMASK_MASK_ALL 0x00000000
174
175/* ECNTRL - ethernet control register */
176#define ECNTRL_CFG_RO 0x80000000 /* GMIIM, RPM, R100M, SGMIIM bits are RO */
177#define ECNTRL_CLRCNT 0x00004000 /* clear all statistics */
178#define ECNTRL_AUTOZ 0x00002000 /* auto zero MIB counter */
179#define ECNTRL_STEN 0x00001000 /* enable internal counters to update */
180#define ECNTRL_GMIIM 0x00000040 /* 1- GMII or RGMII interface mode */
181#define ECNTRL_TBIM 0x00000020 /* 1- Ten-bit interface mode */
182#define ECNTRL_RPM 0x00000010 /* 1- RGMII reduced-pin mode */
183#define ECNTRL_R100M 0x00000008 /* 1- RGMII 100 Mbps, SGMII 100 Mbps
184 0- RGMII 10 Mbps, SGMII 10 Mbps */
185#define ECNTRL_SGMIIM 0x00000002 /* 1- SGMII interface mode */
186#define ECNTRL_TBIM 0x00000020 /* 1- TBI Interface mode (for SGMII) */
187
188#define ECNTRL_DEFAULT (ECNTRL_TBIM | ECNTRL_R100M | ECNTRL_SGMIIM)
189
190/* TCTRL - Transmit control register */
191#define TCTRL_THDF 0x00000800 /* Transmit half-duplex flow control */
192#define TCTRL_TTSE 0x00000040 /* Transmit time-stamp enable */
193#define TCTRL_GTS 0x00000020 /* Graceful transmit stop */
194#define TCTRL_RFC_PAUSE 0x00000010 /* Receive flow control pause frame */
195
196/* RCTRL - Receive control register */
197#define RCTRL_PAL_MASK 0x001f0000 /* packet alignment padding length */
198#define RCTRL_PAL_SHIFT 16
199#define RCTRL_CFA 0x00008000 /* control frame accept enable */
200#define RCTRL_GHTX 0x00000800 /* group address hash table extend */
201#define RCTRL_RTSE 0x00000040 /* receive 1588 time-stamp enable */
202#define RCTRL_GRS 0x00000020 /* graceful receive stop */
203#define RCTRL_BC_REJ 0x00000010 /* broadcast frame reject */
204#define RCTRL_BC_MPROM 0x00000008 /* all multicast/broadcast frames received */
205#define RCTRL_RSF 0x00000004 /* receive short frame(17~63 bytes) enable */
206#define RCTRL_EMEN 0x00000002 /* Exact match MAC address enable */
207#define RCTRL_UPROM 0x00000001 /* all unicast frame received */
208
209/* MACCFG1 - MAC configuration 1 register */
210#define MACCFG1_SOFT_RST 0x80000000 /* place the MAC in reset */
211#define MACCFG1_RST_RXMAC 0x00080000 /* reset receive MAC control block */
212#define MACCFG1_RST_TXMAC 0x00040000 /* reet transmit MAC control block */
213#define MACCFG1_RST_RXFUN 0x00020000 /* reset receive function block */
214#define MACCFG1_RST_TXFUN 0x00010000 /* reset transmit function block */
215#define MACCFG1_LOOPBACK 0x00000100 /* MAC loopback */
216#define MACCFG1_RX_FLOW 0x00000020 /* Receive flow */
217#define MACCFG1_TX_FLOW 0x00000010 /* Transmit flow */
218#define MACCFG1_SYNC_RXEN 0x00000008 /* Frame reception enabled */
219#define MACCFG1_RX_EN 0x00000004 /* Rx enable */
220#define MACCFG1_SYNC_TXEN 0x00000002 /* Frame transmission is enabled */
221#define MACCFG1_TX_EN 0x00000001 /* Tx enable */
222#define MACCFG1_RXTX_EN (MACCFG1_RX_EN | MACCFG1_TX_EN)
223
224/* MACCFG2 - MAC configuration 2 register */
225#define MACCFG2_PRE_LEN_MASK 0x0000f000 /* preamble length */
226#define MACCFG2_PRE_LEN(x) ((x << 12) & MACCFG2_PRE_LEN_MASK)
227#define MACCFG2_IF_MODE_MASK 0x00000300
228#define MACCFG2_IF_MODE_NIBBLE 0x00000100 /* MII, 10/100 Mbps MII/RMII */
229#define MACCFG2_IF_MODE_BYTE 0x00000200 /* GMII/TBI, 1000 GMII/TBI */
230#define MACCFG2_PRE_RX_EN 0x00000080 /* receive preamble enable */
231#define MACCFG2_PRE_TX_EN 0x00000040 /* tx preable enable */
232#define MACCFG2_HUGE_FRAME 0x00000020 /* >= max frame len enable */
233#define MACCFG2_LEN_CHECK 0x00000010 /* MAC check frame's length Rx */
234#define MACCFG2_MAG_EN 0x00000008 /* magic packet enable */
235#define MACCFG2_PAD_CRC 0x00000004 /* pad and append CRC */
236#define MACCFG2_CRC_EN 0x00000002 /* MAC appends a CRC on all frames */
237#define MACCFG2_FULL_DUPLEX 0x00000001 /* Full deplex mode */
238
239struct fsl_enet_mac;
240
241void init_dtsec(struct fsl_enet_mac *mac, void *base, void *phyregs,
242 int max_rx_len);
243
244#endif