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git01.mediatek.com / filogic / uboot / 5ace29c4751f83bfca95f5b14d9e5bd563e0d108 / . / arch / arm / imx-common / speed.c
blob: 638ee1aa75cbcb81ab2b26572cae6dd48f236108 [file] [log] [blame]
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]1/*
2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <asm/arch/imx-regs.h>
Stefano Babicac41d4d2010-03-05 17:54:37 +0100[diff] [blame]29#include <asm/arch/clock.h>
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]30
John Rigby0d21ed02010-12-20 18:27:51 -0700[diff] [blame]31#ifdef CONFIG_FSL_ESDHC
32DECLARE_GLOBAL_DATA_PTR;
33#endif
34
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]35int get_clocks(void)
36{
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]37#ifdef CONFIG_FSL_ESDHC
Michael Langerb2ec8162012-06-14 03:44:33 +0000[diff] [blame]38#ifdef CONFIG_FSL_USDHC
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]39#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]40 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]41#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]42 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]43#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]44 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]45#else
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]46 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]47#endif
Michael Langerb2ec8162012-06-14 03:44:33 +0000[diff] [blame]48#else
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]49#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]50 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]51#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]52 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]53#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]54 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]55#else
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]56 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]57#endif
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]58#endif
Michael Langerb2ec8162012-06-14 03:44:33 +0000[diff] [blame]59#endif
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]60 return 0;
61}