Stephen Warren | 9e54980 | 2015-10-05 12:09:01 -0600 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2014 - 2015 Xilinx, Inc. |
| 3 | * Michal Simek <michal.simek@xilinx.com> |
| 4 | * (This file derived from arch/arm/cpu/armv8/zynqmp/cpu.c) |
| 5 | * |
| 6 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 9 | */ |
| 10 | |
| 11 | #include <common.h> |
| 12 | #include <asm/system.h> |
| 13 | #include <asm/armv8/mmu.h> |
| 14 | |
Alexander Graf | da6cfe1 | 2016-03-04 01:09:50 +0100 | [diff] [blame] | 15 | static struct mm_region tegra_mem_map[] = { |
| 16 | { |
York Sun | c7104e5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 17 | .virt = 0x0UL, |
| 18 | .phys = 0x0UL, |
Alexander Graf | da6cfe1 | 2016-03-04 01:09:50 +0100 | [diff] [blame] | 19 | .size = 0x80000000UL, |
| 20 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 21 | PTE_BLOCK_NON_SHARE | |
| 22 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 23 | }, { |
York Sun | c7104e5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 24 | .virt = 0x80000000UL, |
| 25 | .phys = 0x80000000UL, |
Stephen Warren | fc23c1d | 2016-10-10 09:50:55 -0600 | [diff] [blame] | 26 | .size = 0x80000000UL, |
Alexander Graf | da6cfe1 | 2016-03-04 01:09:50 +0100 | [diff] [blame] | 27 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 28 | PTE_BLOCK_INNER_SHARE |
| 29 | }, { |
| 30 | /* List terminator */ |
| 31 | 0, |
Stephen Warren | 9e54980 | 2015-10-05 12:09:01 -0600 | [diff] [blame] | 32 | } |
Alexander Graf | da6cfe1 | 2016-03-04 01:09:50 +0100 | [diff] [blame] | 33 | }; |
Stephen Warren | 9e54980 | 2015-10-05 12:09:01 -0600 | [diff] [blame] | 34 | |
Alexander Graf | da6cfe1 | 2016-03-04 01:09:50 +0100 | [diff] [blame] | 35 | struct mm_region *mem_map = tegra_mem_map; |