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git01.mediatek.com / filogic / uboot / 5a9d7f10f533430513ab16321886444ee0bf95ef / . / configs / Yones_Toptech_BD1078_defconfig
blob: aab580e05e03a6c6cb6544f4656413467e8c72d7 [file] [log] [blame]
Joe Hershbergera274ded2015-05-12 14:46:24 -0500[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_SUNXI=y
3CONFIG_MACH_SUN7I=y
4CONFIG_DRAM_CLK=408
Paul Kocialkowski794a3d12015-03-29 11:19:45 +0200[diff] [blame]5CONFIG_MMC0_CD_PIN="PH1"
6CONFIG_MMC1_CD_PIN="PH2"
Paul Kocialkowskid1a8d5b2015-03-22 18:12:24 +0100[diff] [blame]7CONFIG_MMC1_PINS="PH"
Joe Hershbergera274ded2015-05-12 14:46:24 -0500[diff] [blame]8CONFIG_MMC_SUNXI_SLOT_EXTRA=1
Paul Kocialkowskid1a8d5b2015-03-22 18:12:24 +0100[diff] [blame]9CONFIG_USB0_VBUS_PIN="PB9"
10CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
Hans de Goede3ae1d132015-04-25 17:25:14 +0200[diff] [blame]11CONFIG_AXP_GPIO=y
Paul Kocialkowskid1a8d5b2015-03-22 18:12:24 +0100[diff] [blame]12CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:63000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
13CONFIG_VIDEO_LCD_DCLK_PHASE=0
Paul Kocialkowskid1a8d5b2015-03-22 18:12:24 +0100[diff] [blame]14CONFIG_VIDEO_LCD_POWER="PH8"
15CONFIG_VIDEO_LCD_BL_EN="PH7"
16CONFIG_VIDEO_LCD_BL_PWM="PB2"
Joe Hershbergera274ded2015-05-12 14:46:24 -0500[diff] [blame]17# CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set
18CONFIG_VIDEO_LCD_PANEL_LVDS=y
19CONFIG_USB_MUSB_SUNXI=y
20CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078"
Joe Hershberger17491a82015-06-22 16:15:29 -0500[diff] [blame]21# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
Joe Hershbergera274ded2015-05-12 14:46:24 -0500[diff] [blame]22CONFIG_SPL=y
23CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame^]24# CONFIG_CMD_IMLS is not set
25# CONFIG_CMD_FLASH is not set
26# CONFIG_CMD_FPGA is not set
Joe Hershberger17491a82015-06-22 16:15:29 -0500[diff] [blame]27CONFIG_DM_ETH=y
Joe Hershberger17491a82015-06-22 16:15:29 -0500[diff] [blame]28CONFIG_DM_SERIAL=y