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git01.mediatek.com / filogic / uboot / 5a90f058f4fbb308ce9052ea5d209d5c6a53f643 / . / arch / arm / dts / imx6q-novena.dts
blob: 35383c9a2b1f9a9bef60b98a9a52c2b2eb778a80 [file] [log] [blame]
Marek Vasutae0cdd02019-05-17 20:32:14 +0200[diff] [blame]1/*
2 * Copyright 2015 Sutajio Ko-Usagi PTE LTD
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 *
47 */
48
49/dts-v1/;
50#include "imx6q.dtsi"
51#include <dt-bindings/gpio/gpio.h>
52#include <dt-bindings/input/input.h>
53
54/ {
55 model = "Kosagi Novena Dual/Quad";
56 compatible = "kosagi,imx6q-novena", "fsl,imx6q";
57
58 /* Will be filled by the bootloader */
59 memory@10000000 {
60 device_type = "memory";
61 reg = <0x10000000 0>;
62 };
63
Marek Vasut91cb3b02019-05-17 20:32:17 +0200[diff] [blame]64 aliases {
65 mmc0 = &usdhc3;
66 mmc1 = &usdhc2;
67 };
68
Marek Vasutae0cdd02019-05-17 20:32:14 +0200[diff] [blame]69 chosen {
70 stdout-path = &uart2;
71 };
72
73 backlight: backlight {
74 compatible = "pwm-backlight";
75 pwms = <&pwm1 0 10000000>;
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_backlight_novena>;
78 power-supply = <&reg_lvds_lcd>;
79 brightness-levels = <0 3 6 12 16 24 32 48 64 96 128 192 255>;
80 default-brightness-level = <12>;
81 };
82
83 gpio-keys {
84 compatible = "gpio-keys";
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_gpio_keys_novena>;
87
88 user-button {
89 label = "User Button";
90 gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
91 linux,code = <KEY_POWER>;
92 };
93
94 lid {
95 label = "Lid";
96 gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
97 linux,input-type = <5>; /* EV_SW */
98 linux,code = <0>; /* SW_LID */
99 };
100 };
101
102 leds {
103 compatible = "gpio-leds";
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_leds_novena>;
106
107 heartbeat {
108 label = "novena:white:panel";
109 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
110 linux,default-trigger = "default-on";
111 };
112 };
113
114 panel: panel {
115 compatible = "innolux,n133hse-ea1", "simple-panel";
116 backlight = <&backlight>;
117 };
118
119 reg_2p5v: regulator-2p5v {
120 compatible = "regulator-fixed";
121 regulator-name = "2P5V";
122 regulator-min-microvolt = <2500000>;
123 regulator-max-microvolt = <2500000>;
124 regulator-always-on;
125 };
126
127 reg_3p3v: regulator-3p3v {
128 compatible = "regulator-fixed";
129 regulator-name = "3P3V";
130 regulator-min-microvolt = <3300000>;
131 regulator-max-microvolt = <3300000>;
132 regulator-always-on;
133 };
134
135 reg_audio_codec: regulator-audio-codec {
136 compatible = "regulator-fixed";
137 regulator-name = "es8328-power";
138 regulator-boot-on;
139 regulator-min-microvolt = <5000000>;
140 regulator-max-microvolt = <5000000>;
141 startup-delay-us = <400000>;
142 gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
143 enable-active-high;
144 };
145
146 reg_display: regulator-display {
147 compatible = "regulator-fixed";
148 regulator-name = "lcd-display-power";
149 regulator-min-microvolt = <3300000>;
150 regulator-max-microvolt = <3300000>;
151 startup-delay-us = <200000>;
152 gpio = <&gpio5 28 GPIO_ACTIVE_HIGH>;
153 enable-active-high;
154 };
155
156 reg_lvds_lcd: regulator-lvds-lcd {
157 compatible = "regulator-fixed";
158 regulator-name = "lcd-lvds-power";
159 regulator-min-microvolt = <3300000>;
160 regulator-max-microvolt = <3300000>;
161 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
162 enable-active-high;
163 };
164
165 reg_pcie: regulator-pcie {
166 compatible = "regulator-fixed";
167 regulator-name = "pcie-bus-power";
168 regulator-min-microvolt = <1500000>;
169 regulator-max-microvolt = <1500000>;
170 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
171 enable-active-high;
172 };
173
174 reg_sata: regulator-sata {
175 compatible = "regulator-fixed";
176 regulator-name = "sata-power";
177 regulator-boot-on;
178 regulator-min-microvolt = <3300000>;
179 regulator-max-microvolt = <3300000>;
180 startup-delay-us = <10000>;
181 gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
182 enable-active-high;
183 };
184
185 reg_usb_otg_vbus: regulator-usb-otg-vbus {
186 compatible = "regulator-fixed";
187 regulator-name = "usb_otg_vbus";
188 regulator-min-microvolt = <5000000>;
189 regulator-max-microvolt = <5000000>;
190 enable-active-high;
191 };
192
193 sound {
194 compatible = "fsl,imx-audio-es8328";
195 model = "imx-audio-es8328";
196 ssi-controller = <&ssi1>;
197 audio-codec = <&codec>;
198 audio-amp-supply = <&reg_audio_codec>;
199 jack-gpio = <&gpio5 15 GPIO_ACTIVE_HIGH>;
200 audio-routing =
201 "Speaker", "LOUT2",
202 "Speaker", "ROUT2",
203 "Speaker", "audio-amp",
204 "Headphone", "ROUT1",
205 "Headphone", "LOUT1",
206 "LINPUT1", "Mic Jack",
207 "RINPUT1", "Mic Jack",
208 "Mic Jack", "Mic Bias";
209 mux-int-port = <0x1>;
210 mux-ext-port = <0x3>;
211 };
212};
213
214&audmux {
215 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_audmux_novena>;
217 status = "okay";
218};
219
220&ecspi3 {
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_ecspi3_novena>;
223 status = "okay";
224};
225
226&fec {
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_enet_novena>;
229 phy-mode = "rgmii";
230 phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
231 rxc-skew-ps = <3000>;
232 rxdv-skew-ps = <0>;
233 txc-skew-ps = <3000>;
234 txen-skew-ps = <0>;
235 rxd0-skew-ps = <0>;
236 rxd1-skew-ps = <0>;
237 rxd2-skew-ps = <0>;
238 rxd3-skew-ps = <0>;
239 txd0-skew-ps = <3000>;
240 txd1-skew-ps = <3000>;
241 txd2-skew-ps = <3000>;
242 txd3-skew-ps = <3000>;
243 status = "okay";
244};
245
246&hdmi {
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_hdmi_novena>;
249 ddc-i2c-bus = <&i2c2>;
250 status = "okay";
251};
252
253&i2c1 {
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_i2c1_novena>;
256 status = "okay";
257
258 accel: mma8452@1c {
259 compatible = "fsl,mma8452";
260 reg = <0x1c>;
261 };
262
263 rtc: pcf8523@68 {
264 compatible = "nxp,pcf8523";
265 reg = <0x68>;
266 };
267
268 sbs_battery: bq20z75@b {
269 compatible = "sbs,sbs-battery";
270 reg = <0x0b>;
271 sbs,i2c-retry-count = <50>;
272 };
273
274 touch: stmpe811@44 {
275 compatible = "st,stmpe811";
276 reg = <0x44>;
277 irq-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>;
278 id = <0>;
279 blocks = <0x5>;
280 irq-trigger = <0x1>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_stmpe_novena>;
283 vio-supply = <&reg_3p3v>;
284 vcc-supply = <&reg_3p3v>;
285
286 stmpe_touchscreen {
287 compatible = "st,stmpe-ts";
288 st,sample-time = <4>;
289 st,mod-12b = <1>;
290 st,ref-sel = <0>;
291 st,adc-freq = <1>;
292 st,ave-ctrl = <1>;
293 st,touch-det-delay = <2>;
294 st,settling = <2>;
295 st,fraction-z = <7>;
296 st,i-drive = <1>;
297 };
298 };
299};
300
301&i2c2 {
302 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_i2c2_novena>;
304 status = "okay";
305
306 pmic: pfuze100@8 {
307 compatible = "fsl,pfuze100";
308 reg = <0x08>;
309
310 regulators {
311 reg_sw1a: sw1a {
312 regulator-min-microvolt = <300000>;
313 regulator-max-microvolt = <1875000>;
314 regulator-boot-on;
315 regulator-always-on;
316 regulator-ramp-delay = <6250>;
317 };
318
319 reg_sw1c: sw1c {
320 regulator-min-microvolt = <300000>;
321 regulator-max-microvolt = <1875000>;
322 regulator-boot-on;
323 regulator-always-on;
324 };
325
326 reg_sw2: sw2 {
327 regulator-min-microvolt = <800000>;
328 regulator-max-microvolt = <3300000>;
329 regulator-boot-on;
330 regulator-always-on;
331 };
332
333 reg_sw3a: sw3a {
334 regulator-min-microvolt = <400000>;
335 regulator-max-microvolt = <1975000>;
336 regulator-boot-on;
337 regulator-always-on;
338 };
339
340 reg_sw3b: sw3b {
341 regulator-min-microvolt = <400000>;
342 regulator-max-microvolt = <1975000>;
343 regulator-boot-on;
344 regulator-always-on;
345 };
346
347 reg_sw4: sw4 {
348 regulator-min-microvolt = <800000>;
349 regulator-max-microvolt = <3300000>;
350 };
351
352 reg_swbst: swbst {
353 regulator-min-microvolt = <5000000>;
354 regulator-max-microvolt = <5150000>;
355 regulator-boot-on;
356 };
357
358 reg_snvs: vsnvs {
359 regulator-min-microvolt = <1000000>;
360 regulator-max-microvolt = <3000000>;
361 regulator-boot-on;
362 regulator-always-on;
363 };
364
365 reg_vref: vrefddr {
366 regulator-boot-on;
367 regulator-always-on;
368 };
369
370 reg_vgen1: vgen1 {
371 regulator-min-microvolt = <800000>;
372 regulator-max-microvolt = <1550000>;
373 };
374
375 reg_vgen2: vgen2 {
376 regulator-min-microvolt = <800000>;
377 regulator-max-microvolt = <1550000>;
378 };
379
380 reg_vgen3: vgen3 {
381 regulator-min-microvolt = <1800000>;
382 regulator-max-microvolt = <3300000>;
383 };
384
385 reg_vgen4: vgen4 {
386 regulator-min-microvolt = <1800000>;
387 regulator-max-microvolt = <3300000>;
388 regulator-always-on;
389 };
390
391 reg_vgen5: vgen5 {
392 regulator-min-microvolt = <1800000>;
393 regulator-max-microvolt = <3300000>;
394 regulator-always-on;
395 };
396
397 reg_vgen6: vgen6 {
398 regulator-min-microvolt = <1800000>;
399 regulator-max-microvolt = <3300000>;
400 regulator-always-on;
401 };
402 };
403 };
404};
405
406&i2c3 {
407 pinctrl-names = "default";
408 pinctrl-0 = <&pinctrl_i2c3_novena>;
409 status = "okay";
410
411 codec: es8328@11 {
412 compatible = "everest,es8328";
413 reg = <0x11>;
414 DVDD-supply = <&reg_audio_codec>;
415 AVDD-supply = <&reg_audio_codec>;
416 PVDD-supply = <&reg_audio_codec>;
417 HPVDD-supply = <&reg_audio_codec>;
418 pinctrl-names = "default";
419 pinctrl-0 = <&pinctrl_sound_novena>;
420 clocks = <&clks IMX6QDL_CLK_CKO1>;
421 assigned-clocks = <&clks IMX6QDL_CLK_CKO>,
422 <&clks IMX6QDL_CLK_CKO1_SEL>,
423 <&clks IMX6QDL_CLK_PLL4_AUDIO>,
424 <&clks IMX6QDL_CLK_CKO1>;
425 assigned-clock-parents = <&clks IMX6QDL_CLK_CKO1>,
426 <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>,
427 <&clks IMX6QDL_CLK_OSC>,
428 <&clks IMX6QDL_CLK_CKO1_PODF>;
429 assigned-clock-rates = <0 0 722534400 22579200>;
430 };
431};
432
433&kpp {
434 pinctrl-names = "default";
435 pinctrl-0 = <&pinctrl_kpp_novena>;
436 linux,keymap = <
437 MATRIX_KEY(1, 1, KEY_CONFIG)
438 >;
439 status = "okay";
440};
441
442&ldb {
443 fsl,dual-channel;
444 status = "okay";
445
446 lvds-channel@0 {
447 fsl,data-mapping = "jeida";
448 fsl,data-width = <24>;
449 fsl,panel = <&panel>;
450 status = "okay";
451 };
452};
453
454&pcie {
455 pinctrl-names = "default";
456 pinctrl-0 = <&pinctrl_pcie_novena>;
457 reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>;
458 vpcie-supply = <&reg_pcie>;
459 status = "okay";
460};
461
462&pwm1 {
463 status = "okay";
464};
465
466&sata {
467 target-supply = <&reg_sata>;
468 fsl,transmit-level-mV = <1025>;
469 fsl,transmit-boost-mdB = <0>;
470 fsl,transmit-atten-16ths = <8>;
471 status = "okay";
472};
473
474&ssi1 {
475 status = "okay";
476};
477
478&uart2 {
479 pinctrl-names = "default";
480 pinctrl-0 = <&pinctrl_uart2_novena>;
481 status = "okay";
482};
483
484&uart3 {
485 pinctrl-names = "default";
486 pinctrl-0 = <&pinctrl_uart3_novena>;
487 status = "okay";
488};
489
490&uart4 {
491 pinctrl-names = "default";
492 pinctrl-0 = <&pinctrl_uart4_novena>;
493 status = "okay";
494};
495
496&usbotg {
497 vbus-supply = <&reg_usb_otg_vbus>;
498 dr_mode = "otg";
499 pinctrl-names = "default";
500 pinctrl-0 = <&pinctrl_usbotg_novena>;
501 disable-over-current;
502 status = "okay";
503};
504
505&usbh1 {
506 vbus-supply = <&reg_swbst>;
507 status = "okay";
508};
509
510&usdhc2 {
511 pinctrl-names = "default";
512 pinctrl-0 = <&pinctrl_usdhc2_novena>;
513 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
514 wp-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
515 bus-width = <4>;
516 status = "okay";
517};
518
519&usdhc3 {
520 pinctrl-names = "default";
521 pinctrl-0 = <&pinctrl_usdhc3_novena>;
522 bus-width = <4>;
523 non-removable;
524 status = "okay";
525};
526
527&iomuxc {
528 pinctrl_audmux_novena: audmuxgrp-novena {
529 fsl,pins = <
530 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
531 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
532 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
533 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
534 >;
535 };
536
537 pinctrl_backlight_novena: backlightgrp-novena {
538 fsl,pins = <
539 MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0
540 MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b1
541 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1
542 >;
543 };
544
545 pinctrl_ecspi3_novena: ecspi3grp-novena {
546 fsl,pins = <
547 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
548 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
549 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
550 >;
551 };
552
553 pinctrl_enet_novena: enetgrp-novena {
554 fsl,pins = <
555 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
556 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
557 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020
558 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b028
559 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b028
560 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b028
561 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b028
562 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b028
563 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
564 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
565 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
566 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
567 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
568 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
569 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
570 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
571 /* Ethernet reset */
572 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b1
573 >;
574 };
575
576 pinctrl_fpga_gpio: fpgagpiogrp-novena {
577 fsl,pins = <
578 /* FPGA power */
579 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b1
580 /* Reset */
581 MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1
582 /* FPGA GPIOs */
583 MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1
584 MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1
585 MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1
586 MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1
587 MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1
588 MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1
589 MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1
590 MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1
591 MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1
592 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1
593 MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1
594 MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1
595 MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1
596 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1
597 MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1
598 MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1
599 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1
600 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b1
601 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1
602 MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1
603 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1
604 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1
605 MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1
606 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1
607 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1
608 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1
609 >;
610 };
611
612 pinctrl_fpga_eim: fpgaeimgrp-novena {
613 fsl,pins = <
614 /* FPGA power */
615 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b1
616 /* Reset */
617 MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1
618 /* FPGA GPIOs */
619 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0f1
620 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0f1
621 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0f1
622 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0f1
623 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0f1
624 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0f1
625 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0f1
626 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0f1
627 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0f1
628 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0f1
629 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0f1
630 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0f1
631 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0f1
632 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0f1
633 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0f1
634 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0f1
635 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0f1
636 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0f1
637 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0f1
638 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0f1
639 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0f1
640 MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb0f1
641 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0f1
642 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0f1
643 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb0f1
644 MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0xb0f1
645 >;
646 };
647
648 pinctrl_gpio_keys_novena: gpiokeysgrp-novena {
649 fsl,pins = <
650 /* User button */
651 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
652 /* PCIe Wakeup */
653 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1f0e0
654 /* Lid switch */
655 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0
656 >;
657 };
658
659 pinctrl_hdmi_novena: hdmigrp-novena {
660 fsl,pins = <
661 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
662 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1
663 >;
664 };
665
666 pinctrl_i2c1_novena: i2c1grp-novena {
667 fsl,pins = <
668 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
669 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
670 >;
671 };
672
673 pinctrl_i2c2_novena: i2c2grp-novena {
674 fsl,pins = <
675 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
676 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
677 >;
678 };
679
680 pinctrl_i2c3_novena: i2c3grp-novena {
681 fsl,pins = <
682 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
683 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
684 >;
685 };
686
687 pinctrl_kpp_novena: kppgrp-novena {
688 fsl,pins = <
689 /* Front panel button */
690 MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x1b0b1
691 /* Fake column driver, not connected */
692 MX6QDL_PAD_KEY_COL1__KEY_COL1 0x1b0b1
693 >;
694 };
695
696 pinctrl_leds_novena: ledsgrp-novena {
697 fsl,pins = <
698 MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b1
699 >;
700 };
701
702 pinctrl_pcie_novena: pciegrp-novena {
703 fsl,pins = <
704 /* Reset */
705 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1
706 /* Power On */
707 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1
708 /* Wifi kill */
709 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1
710 >;
711 };
712
713 pinctrl_sata_novena: satagrp-novena {
714 fsl,pins = <
715 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b1
716 >;
717 };
718
719 pinctrl_senoko_novena: senokogrp-novena {
720 fsl,pins = <
721 /* Senoko IRQ line */
722 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x13048
723 /* Senoko reset line */
724 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1
725 >;
726 };
727
728 pinctrl_sound_novena: soundgrp-novena {
729 fsl,pins = <
730 /* Audio power regulator */
731 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1
732 /* Headphone plug */
733 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1
734 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
735 >;
736 };
737
738 pinctrl_stmpe_novena: stmpegrp-novena {
739 fsl,pins = <
740 /* Touchscreen interrupt */
741 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1
742 >;
743 };
744
745 pinctrl_uart2_novena: uart2grp-novena {
746 fsl,pins = <
747 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
748 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
749 >;
750 };
751
752 pinctrl_uart3_novena: uart3grp-novena {
753 fsl,pins = <
754 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
755 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
756 >;
757 };
758
759 pinctrl_uart4_novena: uart4grp-novena {
760 fsl,pins = <
761 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
762 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
763 >;
764 };
765
766 pinctrl_usbotg_novena: usbotggrp-novena {
767 fsl,pins = <
768 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
769 >;
770 };
771
772 pinctrl_usdhc2_novena: usdhc2grp-novena {
773 fsl,pins = <
774 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
775 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
776 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
777 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
778 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
779 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
780 /* Write protect */
781 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
782 /* Card detect */
783 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1
784 >;
785 };
786
787 pinctrl_usdhc3_novena: usdhc3grp-novena {
788 fsl,pins = <
789 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
790 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
791 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
792 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
793 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
794 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
795 >;
796 };
797};