Rajesh Bhagat | 45d8a54 | 2018-11-05 18:03:04 +0000 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_TARGET_LS1012AQDS=y |
| 3 | CONFIG_SYS_TEXT_BASE=0x82000000 |
| 4 | CONFIG_QSPI_AHB_INIT=y |
| 5 | CONFIG_TFABOOT=y |
| 6 | CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y |
| 7 | CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y |
| 8 | CONFIG_AHCI=y |
| 9 | CONFIG_DISTRO_DEFAULTS=y |
| 10 | CONFIG_NR_DRAM_BANKS=2 |
| 11 | # CONFIG_SYS_MALLOC_F is not set |
| 12 | CONFIG_FIT_VERBOSE=y |
| 13 | CONFIG_OF_BOARD_SETUP=y |
| 14 | CONFIG_OF_STDOUT_VIA_ALIAS=y |
| 15 | CONFIG_BOOTDELAY=10 |
| 16 | CONFIG_USE_BOOTARGS=y |
| 17 | CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" |
| 18 | # CONFIG_USE_BOOTCOMMAND is not set |
| 19 | CONFIG_MISC_INIT_R=y |
| 20 | # CONFIG_DISPLAY_BOARDINFO is not set |
| 21 | CONFIG_DISPLAY_BOARDINFO_LATE=y |
| 22 | CONFIG_CMD_GREPENV=y |
| 23 | CONFIG_CMD_EEPROM=y |
| 24 | CONFIG_CMD_MEMTEST=y |
| 25 | CONFIG_CMD_GPT=y |
| 26 | CONFIG_CMD_I2C=y |
| 27 | CONFIG_CMD_MMC=y |
| 28 | CONFIG_CMD_PCI=y |
| 29 | CONFIG_CMD_SF=y |
Patrick Delaunay | 5a6b52b | 2019-02-27 15:20:37 +0100 | [diff] [blame^] | 30 | CONFIG_CMD_SPI=y |
| 31 | CONFIG_DEFAULT_SPI_BUS=1 |
Rajesh Bhagat | 45d8a54 | 2018-11-05 18:03:04 +0000 | [diff] [blame] | 32 | CONFIG_CMD_USB=y |
| 33 | # CONFIG_CMD_SETEXPR is not set |
| 34 | CONFIG_CMD_CACHE=y |
| 35 | CONFIG_CMD_DATE=y |
| 36 | CONFIG_OF_CONTROL=y |
| 37 | CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" |
| 38 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 39 | CONFIG_NET_RANDOM_ETHADDR=y |
| 40 | CONFIG_DM=y |
| 41 | CONFIG_SCSI_AHCI=y |
| 42 | CONFIG_SATA_CEVA=y |
| 43 | CONFIG_DM_MMC=y |
| 44 | CONFIG_FSL_ESDHC=y |
| 45 | CONFIG_DM_SPI_FLASH=y |
| 46 | CONFIG_SPI_FLASH=y |
Patrick Delaunay | 0df8104 | 2019-02-27 15:20:36 +0100 | [diff] [blame] | 47 | CONFIG_SF_DEFAULT_BUS=1 |
| 48 | CONFIG_SF_DEFAULT_MODE=0 |
| 49 | CONFIG_SF_DEFAULT_SPEED=10000000 |
Rajesh Bhagat | 45d8a54 | 2018-11-05 18:03:04 +0000 | [diff] [blame] | 50 | # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set |
| 51 | CONFIG_FSL_PFE=y |
| 52 | CONFIG_DM_ETH=y |
| 53 | CONFIG_E1000=y |
| 54 | CONFIG_PCI=y |
| 55 | CONFIG_DM_PCI=y |
| 56 | CONFIG_DM_PCI_COMPAT=y |
| 57 | CONFIG_PCIE_LAYERSCAPE=y |
| 58 | CONFIG_SCSI=y |
| 59 | CONFIG_DM_SCSI=y |
| 60 | CONFIG_SYS_NS16550=y |
| 61 | CONFIG_SPI=y |
| 62 | CONFIG_DM_SPI=y |
| 63 | CONFIG_FSL_DSPI=y |
| 64 | CONFIG_USB=y |
| 65 | CONFIG_DM_USB=y |
| 66 | CONFIG_USB_XHCI_HCD=y |
| 67 | CONFIG_USB_XHCI_DWC3=y |