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git01.mediatek.com / filogic / uboot / 5a1d96886a074a7d22a4e968364e150f59649f3c / . / dts / upstream / src / arm / st / stm32h743.dtsi
blob: b8d4c44c8a82a9058e7cb27ba15246a796556028 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1/*
2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "../armv7-m.dtsi"
44#include <dt-bindings/clock/stm32h7-clks.h>
45#include <dt-bindings/mfd/stm32h7-rcc.h>
46#include <dt-bindings/interrupt-controller/irq.h>
47
48/ {
49 #address-cells = <1>;
50 #size-cells = <1>;
51
52 clocks {
53 clk_hse: clk-hse {
54 #clock-cells = <0>;
55 compatible = "fixed-clock";
56 clock-frequency = <0>;
57 };
58
59 clk_lse: clk-lse {
60 #clock-cells = <0>;
61 compatible = "fixed-clock";
62 clock-frequency = <32768>;
63 };
64
65 clk_i2s: i2s_ckin {
66 #clock-cells = <0>;
67 compatible = "fixed-clock";
68 clock-frequency = <0>;
69 };
70 };
71
72 soc {
73 timer5: timer@40000c00 {
74 compatible = "st,stm32-timer";
75 reg = <0x40000c00 0x400>;
76 interrupts = <50>;
77 clocks = <&rcc TIM5_CK>;
78 };
79
80 lptimer1: timer@40002400 {
81 #address-cells = <1>;
82 #size-cells = <0>;
83 compatible = "st,stm32-lptimer";
84 reg = <0x40002400 0x400>;
85 clocks = <&rcc LPTIM1_CK>;
86 clock-names = "mux";
87 status = "disabled";
88
89 pwm {
90 compatible = "st,stm32-pwm-lp";
91 #pwm-cells = <3>;
92 status = "disabled";
93 };
94
95 trigger@0 {
96 compatible = "st,stm32-lptimer-trigger";
97 reg = <0>;
98 status = "disabled";
99 };
100
101 counter {
102 compatible = "st,stm32-lptimer-counter";
103 status = "disabled";
104 };
105 };
106
107 spi2: spi@40003800 {
108 #address-cells = <1>;
109 #size-cells = <0>;
110 compatible = "st,stm32h7-spi";
111 reg = <0x40003800 0x400>;
112 interrupts = <36>;
113 resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
114 clocks = <&rcc SPI2_CK>;
115 status = "disabled";
116
117 };
118
119 spi3: spi@40003c00 {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 compatible = "st,stm32h7-spi";
123 reg = <0x40003c00 0x400>;
124 interrupts = <51>;
125 resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
126 clocks = <&rcc SPI3_CK>;
127 status = "disabled";
128 };
129
130 usart2: serial@40004400 {
131 compatible = "st,stm32h7-uart";
132 reg = <0x40004400 0x400>;
133 interrupts = <38>;
134 status = "disabled";
135 clocks = <&rcc USART2_CK>;
136 };
137
138 usart3: serial@40004800 {
139 compatible = "st,stm32h7-uart";
140 reg = <0x40004800 0x400>;
141 interrupts = <39>;
142 status = "disabled";
143 clocks = <&rcc USART3_CK>;
144 };
145
146 uart4: serial@40004c00 {
147 compatible = "st,stm32h7-uart";
148 reg = <0x40004c00 0x400>;
149 interrupts = <52>;
150 status = "disabled";
151 clocks = <&rcc UART4_CK>;
152 };
153
154 i2c1: i2c@40005400 {
155 compatible = "st,stm32f7-i2c";
156 #address-cells = <1>;
157 #size-cells = <0>;
158 reg = <0x40005400 0x400>;
159 interrupts = <31>,
160 <32>;
161 resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
162 clocks = <&rcc I2C1_CK>;
163 status = "disabled";
164 };
165
166 i2c2: i2c@40005800 {
167 compatible = "st,stm32f7-i2c";
168 #address-cells = <1>;
169 #size-cells = <0>;
170 reg = <0x40005800 0x400>;
171 interrupts = <33>,
172 <34>;
173 resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
174 clocks = <&rcc I2C2_CK>;
175 status = "disabled";
176 };
177
178 i2c3: i2c@40005c00 {
179 compatible = "st,stm32f7-i2c";
180 #address-cells = <1>;
181 #size-cells = <0>;
182 reg = <0x40005C00 0x400>;
183 interrupts = <72>,
184 <73>;
185 resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
186 clocks = <&rcc I2C3_CK>;
187 status = "disabled";
188 };
189
190 dac: dac@40007400 {
191 compatible = "st,stm32h7-dac-core";
192 reg = <0x40007400 0x400>;
193 clocks = <&rcc DAC12_CK>;
194 clock-names = "pclk";
195 #address-cells = <1>;
196 #size-cells = <0>;
197 status = "disabled";
198
199 dac1: dac@1 {
200 compatible = "st,stm32-dac";
201 #io-channel-cells = <1>;
202 reg = <1>;
203 status = "disabled";
204 };
205
206 dac2: dac@2 {
207 compatible = "st,stm32-dac";
208 #io-channel-cells = <1>;
209 reg = <2>;
210 status = "disabled";
211 };
212 };
213
214 usart1: serial@40011000 {
215 compatible = "st,stm32h7-uart";
216 reg = <0x40011000 0x400>;
217 interrupts = <37>;
218 status = "disabled";
219 clocks = <&rcc USART1_CK>;
220 };
221
222 spi1: spi@40013000 {
223 #address-cells = <1>;
224 #size-cells = <0>;
225 compatible = "st,stm32h7-spi";
226 reg = <0x40013000 0x400>;
227 interrupts = <35>;
228 resets = <&rcc STM32H7_APB2_RESET(SPI1)>;
229 clocks = <&rcc SPI1_CK>;
230 status = "disabled";
231 };
232
233 spi4: spi@40013400 {
234 #address-cells = <1>;
235 #size-cells = <0>;
236 compatible = "st,stm32h7-spi";
237 reg = <0x40013400 0x400>;
238 interrupts = <84>;
239 resets = <&rcc STM32H7_APB2_RESET(SPI4)>;
240 clocks = <&rcc SPI4_CK>;
241 status = "disabled";
242 };
243
244 spi5: spi@40015000 {
245 #address-cells = <1>;
246 #size-cells = <0>;
247 compatible = "st,stm32h7-spi";
248 reg = <0x40015000 0x400>;
249 interrupts = <85>;
250 resets = <&rcc STM32H7_APB2_RESET(SPI5)>;
251 clocks = <&rcc SPI5_CK>;
252 status = "disabled";
253 };
254
255 dma1: dma-controller@40020000 {
256 compatible = "st,stm32-dma";
257 reg = <0x40020000 0x400>;
258 interrupts = <11>,
259 <12>,
260 <13>,
261 <14>,
262 <15>,
263 <16>,
264 <17>,
265 <47>;
266 clocks = <&rcc DMA1_CK>;
267 #dma-cells = <4>;
268 st,mem2mem;
269 dma-requests = <8>;
270 status = "disabled";
271 };
272
273 dma2: dma-controller@40020400 {
274 compatible = "st,stm32-dma";
275 reg = <0x40020400 0x400>;
276 interrupts = <56>,
277 <57>,
278 <58>,
279 <59>,
280 <60>,
281 <68>,
282 <69>,
283 <70>;
284 clocks = <&rcc DMA2_CK>;
285 #dma-cells = <4>;
286 st,mem2mem;
287 dma-requests = <8>;
288 status = "disabled";
289 };
290
291 dmamux1: dma-router@40020800 {
292 compatible = "st,stm32h7-dmamux";
293 reg = <0x40020800 0x40>;
294 #dma-cells = <3>;
295 dma-channels = <16>;
296 dma-requests = <128>;
297 dma-masters = <&dma1 &dma2>;
298 clocks = <&rcc DMA1_CK>;
299 };
300
301 adc_12: adc@40022000 {
302 compatible = "st,stm32h7-adc-core";
303 reg = <0x40022000 0x400>;
304 interrupts = <18>;
305 clocks = <&rcc ADC12_CK>;
306 clock-names = "bus";
307 interrupt-controller;
308 #interrupt-cells = <1>;
309 #address-cells = <1>;
310 #size-cells = <0>;
311 status = "disabled";
312
313 adc1: adc@0 {
314 compatible = "st,stm32h7-adc";
315 #io-channel-cells = <1>;
316 reg = <0x0>;
317 interrupt-parent = <&adc_12>;
318 interrupts = <0>;
319 status = "disabled";
320 };
321
322 adc2: adc@100 {
323 compatible = "st,stm32h7-adc";
324 #io-channel-cells = <1>;
325 reg = <0x100>;
326 interrupt-parent = <&adc_12>;
327 interrupts = <1>;
328 status = "disabled";
329 };
330 };
331
332 usbotg_hs: usb@40040000 {
333 compatible = "st,stm32f7-hsotg";
334 reg = <0x40040000 0x40000>;
335 interrupts = <77>;
336 clocks = <&rcc USB1OTG_CK>;
337 clock-names = "otg";
338 g-rx-fifo-size = <256>;
339 g-np-tx-fifo-size = <32>;
340 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
341 status = "disabled";
342 };
343
344 usbotg_fs: usb@40080000 {
345 compatible = "st,stm32f4x9-fsotg";
346 reg = <0x40080000 0x40000>;
347 interrupts = <101>;
348 clocks = <&rcc USB2OTG_CK>;
349 clock-names = "otg";
350 status = "disabled";
351 };
352
353 ltdc: display-controller@50001000 {
354 compatible = "st,stm32-ltdc";
355 reg = <0x50001000 0x200>;
356 interrupts = <88>, <89>;
357 resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
358 clocks = <&rcc LTDC_CK>;
359 clock-names = "lcd";
360 status = "disabled";
361 };
362
363 mdma1: dma-controller@52000000 {
364 compatible = "st,stm32h7-mdma";
365 reg = <0x52000000 0x1000>;
366 interrupts = <122>;
367 clocks = <&rcc MDMA_CK>;
368 #dma-cells = <5>;
369 dma-channels = <16>;
370 dma-requests = <32>;
371 };
372
373 sdmmc1: mmc@52007000 {
374 compatible = "arm,pl18x", "arm,primecell";
375 arm,primecell-periphid = <0x10153180>;
376 reg = <0x52007000 0x1000>;
377 interrupts = <49>;
378 clocks = <&rcc SDMMC1_CK>;
379 clock-names = "apb_pclk";
380 resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
381 cap-sd-highspeed;
382 cap-mmc-highspeed;
383 max-frequency = <120000000>;
384 };
385
386 sdmmc2: mmc@48022400 {
387 compatible = "arm,pl18x", "arm,primecell";
388 arm,primecell-periphid = <0x10153180>;
389 reg = <0x48022400 0x400>;
390 interrupts = <124>;
391 clocks = <&rcc SDMMC2_CK>;
392 clock-names = "apb_pclk";
393 resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
394 cap-sd-highspeed;
395 cap-mmc-highspeed;
396 max-frequency = <120000000>;
397 status = "disabled";
398 };
399
400 exti: interrupt-controller@58000000 {
401 compatible = "st,stm32h7-exti";
402 interrupt-controller;
403 #interrupt-cells = <2>;
404 reg = <0x58000000 0x400>;
405 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
406 };
407
408 syscfg: syscon@58000400 {
409 compatible = "st,stm32-syscfg", "syscon";
410 reg = <0x58000400 0x400>;
411 };
412
413 spi6: spi@58001400 {
414 #address-cells = <1>;
415 #size-cells = <0>;
416 compatible = "st,stm32h7-spi";
417 reg = <0x58001400 0x400>;
418 interrupts = <86>;
419 resets = <&rcc STM32H7_APB4_RESET(SPI6)>;
420 clocks = <&rcc SPI6_CK>;
421 status = "disabled";
422 };
423
424 i2c4: i2c@58001c00 {
425 compatible = "st,stm32f7-i2c";
426 #address-cells = <1>;
427 #size-cells = <0>;
428 reg = <0x58001C00 0x400>;
429 interrupts = <95>,
430 <96>;
431 resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
432 clocks = <&rcc I2C4_CK>;
433 status = "disabled";
434 };
435
436 lptimer2: timer@58002400 {
437 #address-cells = <1>;
438 #size-cells = <0>;
439 compatible = "st,stm32-lptimer";
440 reg = <0x58002400 0x400>;
441 clocks = <&rcc LPTIM2_CK>;
442 clock-names = "mux";
443 status = "disabled";
444
445 pwm {
446 compatible = "st,stm32-pwm-lp";
447 #pwm-cells = <3>;
448 status = "disabled";
449 };
450
451 trigger@1 {
452 compatible = "st,stm32-lptimer-trigger";
453 reg = <1>;
454 status = "disabled";
455 };
456
457 counter {
458 compatible = "st,stm32-lptimer-counter";
459 status = "disabled";
460 };
461 };
462
463 lptimer3: timer@58002800 {
464 #address-cells = <1>;
465 #size-cells = <0>;
466 compatible = "st,stm32-lptimer";
467 reg = <0x58002800 0x400>;
468 clocks = <&rcc LPTIM3_CK>;
469 clock-names = "mux";
470 status = "disabled";
471
472 pwm {
473 compatible = "st,stm32-pwm-lp";
474 #pwm-cells = <3>;
475 status = "disabled";
476 };
477
478 trigger@2 {
479 compatible = "st,stm32-lptimer-trigger";
480 reg = <2>;
481 status = "disabled";
482 };
483 };
484
485 lptimer4: timer@58002c00 {
486 compatible = "st,stm32-lptimer";
487 reg = <0x58002c00 0x400>;
488 clocks = <&rcc LPTIM4_CK>;
489 clock-names = "mux";
490 status = "disabled";
491
492 pwm {
493 compatible = "st,stm32-pwm-lp";
494 #pwm-cells = <3>;
495 status = "disabled";
496 };
497 };
498
499 lptimer5: timer@58003000 {
500 compatible = "st,stm32-lptimer";
501 reg = <0x58003000 0x400>;
502 clocks = <&rcc LPTIM5_CK>;
503 clock-names = "mux";
504 status = "disabled";
505
506 pwm {
507 compatible = "st,stm32-pwm-lp";
508 #pwm-cells = <3>;
509 status = "disabled";
510 };
511 };
512
513 vrefbuf: regulator@58003c00 {
514 compatible = "st,stm32-vrefbuf";
515 reg = <0x58003C00 0x8>;
516 clocks = <&rcc VREF_CK>;
517 regulator-min-microvolt = <1500000>;
518 regulator-max-microvolt = <2500000>;
519 status = "disabled";
520 };
521
522 rtc: rtc@58004000 {
523 compatible = "st,stm32h7-rtc";
524 reg = <0x58004000 0x400>;
525 clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
526 clock-names = "pclk", "rtc_ck";
527 assigned-clocks = <&rcc RTC_CK>;
528 assigned-clock-parents = <&rcc LSE_CK>;
529 interrupt-parent = <&exti>;
530 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
531 st,syscfg = <&pwrcfg 0x00 0x100>;
532 status = "disabled";
533 };
534
535 rcc: reset-clock-controller@58024400 {
536 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
537 reg = <0x58024400 0x400>;
538 #clock-cells = <1>;
539 #reset-cells = <1>;
540 clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
541 st,syscfg = <&pwrcfg>;
542 };
543
544 pwrcfg: power-config@58024800 {
545 compatible = "st,stm32-power-config", "syscon";
546 reg = <0x58024800 0x400>;
547 };
548
549 adc_3: adc@58026000 {
550 compatible = "st,stm32h7-adc-core";
551 reg = <0x58026000 0x400>;
552 interrupts = <127>;
553 clocks = <&rcc ADC3_CK>;
554 clock-names = "bus";
555 interrupt-controller;
556 #interrupt-cells = <1>;
557 #address-cells = <1>;
558 #size-cells = <0>;
559 status = "disabled";
560
561 adc3: adc@0 {
562 compatible = "st,stm32h7-adc";
563 #io-channel-cells = <1>;
564 reg = <0x0>;
565 interrupt-parent = <&adc_3>;
566 interrupts = <0>;
567 status = "disabled";
568 };
569 };
570
571 mac: ethernet@40028000 {
572 compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
573 reg = <0x40028000 0x8000>;
574 reg-names = "stmmaceth";
575 interrupts = <61>;
576 interrupt-names = "macirq";
577 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
578 clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>;
579 st,syscon = <&syscfg 0x4>;
580 snps,pbl = <8>;
581 status = "disabled";
582 };
583
584 pinctrl: pinctrl@58020000 {
585 #address-cells = <1>;
586 #size-cells = <1>;
587 compatible = "st,stm32h743-pinctrl";
588 ranges = <0 0x58020000 0x3000>;
589 interrupt-parent = <&exti>;
590 st,syscfg = <&syscfg 0x8>;
591
592 gpioa: gpio@58020000 {
593 gpio-controller;
594 #gpio-cells = <2>;
595 reg = <0x0 0x400>;
596 clocks = <&rcc GPIOA_CK>;
597 st,bank-name = "GPIOA";
598 interrupt-controller;
599 #interrupt-cells = <2>;
600 ngpios = <16>;
601 gpio-ranges = <&pinctrl 0 0 16>;
602 };
603
604 gpiob: gpio@58020400 {
605 gpio-controller;
606 #gpio-cells = <2>;
607 reg = <0x400 0x400>;
608 clocks = <&rcc GPIOB_CK>;
609 st,bank-name = "GPIOB";
610 interrupt-controller;
611 #interrupt-cells = <2>;
612 ngpios = <16>;
613 gpio-ranges = <&pinctrl 0 16 16>;
614 };
615
616 gpioc: gpio@58020800 {
617 gpio-controller;
618 #gpio-cells = <2>;
619 reg = <0x800 0x400>;
620 clocks = <&rcc GPIOC_CK>;
621 st,bank-name = "GPIOC";
622 interrupt-controller;
623 #interrupt-cells = <2>;
624 ngpios = <16>;
625 gpio-ranges = <&pinctrl 0 32 16>;
626 };
627
628 gpiod: gpio@58020c00 {
629 gpio-controller;
630 #gpio-cells = <2>;
631 reg = <0xc00 0x400>;
632 clocks = <&rcc GPIOD_CK>;
633 st,bank-name = "GPIOD";
634 interrupt-controller;
635 #interrupt-cells = <2>;
636 ngpios = <16>;
637 gpio-ranges = <&pinctrl 0 48 16>;
638 };
639
640 gpioe: gpio@58021000 {
641 gpio-controller;
642 #gpio-cells = <2>;
643 reg = <0x1000 0x400>;
644 clocks = <&rcc GPIOE_CK>;
645 st,bank-name = "GPIOE";
646 interrupt-controller;
647 #interrupt-cells = <2>;
648 ngpios = <16>;
649 gpio-ranges = <&pinctrl 0 64 16>;
650 };
651
652 gpiof: gpio@58021400 {
653 gpio-controller;
654 #gpio-cells = <2>;
655 reg = <0x1400 0x400>;
656 clocks = <&rcc GPIOF_CK>;
657 st,bank-name = "GPIOF";
658 interrupt-controller;
659 #interrupt-cells = <2>;
660 ngpios = <16>;
661 gpio-ranges = <&pinctrl 0 80 16>;
662 };
663
664 gpiog: gpio@58021800 {
665 gpio-controller;
666 #gpio-cells = <2>;
667 reg = <0x1800 0x400>;
668 clocks = <&rcc GPIOG_CK>;
669 st,bank-name = "GPIOG";
670 interrupt-controller;
671 #interrupt-cells = <2>;
672 ngpios = <16>;
673 gpio-ranges = <&pinctrl 0 96 16>;
674 };
675
676 gpioh: gpio@58021c00 {
677 gpio-controller;
678 #gpio-cells = <2>;
679 reg = <0x1c00 0x400>;
680 clocks = <&rcc GPIOH_CK>;
681 st,bank-name = "GPIOH";
682 interrupt-controller;
683 #interrupt-cells = <2>;
684 ngpios = <16>;
685 gpio-ranges = <&pinctrl 0 112 16>;
686 };
687
688 gpioi: gpio@58022000 {
689 gpio-controller;
690 #gpio-cells = <2>;
691 reg = <0x2000 0x400>;
692 clocks = <&rcc GPIOI_CK>;
693 st,bank-name = "GPIOI";
694 interrupt-controller;
695 #interrupt-cells = <2>;
696 ngpios = <16>;
697 gpio-ranges = <&pinctrl 0 128 16>;
698 };
699
700 gpioj: gpio@58022400 {
701 gpio-controller;
702 #gpio-cells = <2>;
703 reg = <0x2400 0x400>;
704 clocks = <&rcc GPIOJ_CK>;
705 st,bank-name = "GPIOJ";
706 interrupt-controller;
707 #interrupt-cells = <2>;
708 ngpios = <16>;
709 gpio-ranges = <&pinctrl 0 144 16>;
710 };
711
712 gpiok: gpio@58022800 {
713 gpio-controller;
714 #gpio-cells = <2>;
715 reg = <0x2800 0x400>;
716 clocks = <&rcc GPIOK_CK>;
717 st,bank-name = "GPIOK";
718 interrupt-controller;
719 #interrupt-cells = <2>;
720 ngpios = <8>;
721 gpio-ranges = <&pinctrl 0 160 8>;
722 };
723 };
724 };
725};
726
727&systick {
728 clock-frequency = <250000000>;
729 status = "okay";
730};